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1.发明授权Standard cell array having fake gate for isolating devices from supply voltages 失效具有用于将器件与电源电压隔离的假栅极的标准单元阵列
公开(公告)号：US4851892A
公开(公告)日：1989-07-25
申请号：US94246
申请日：1987-09-08
IPC分类号： H01L21/765 , H01L27/118
CPC分类号： H01L27/11807 , H01L21/765
摘要： A standard cell array is disclosed having improved device isolation, customized metal routing under power busses, a gate array core cell having improved internal routing channels, and shared power busses. A fake gate is located adjacent a source of drain of a transistor within each cell, and is coupled to a supply voltage for isolating the transistors within each cell. Additional metallization strips partially overlap and extend between adjacent rows and columns, respectively, of the core cells for providing supply voltages thereto. Further metallization strips for conducting signals overlie the internal portion of the core cell and extend the entire length of the row or column of core cells.
摘要翻译： 公开了一种标准单元阵列，其具有改进的器件隔离，功率总线下的定制金属布线，具有改进的内部布线通道的门阵列核心单元和共享功率总线。 假栅极位于每个单元内的晶体管的漏极源附近，并且耦合到用于隔离每个单元中的晶体管的电源电压。 另外的金属化条分别在芯单元的相邻行和列之间部分地重叠并延伸，以便向其提供电源电压。 用于传导信号的另外的金属化条覆盖在核心单元的内部部分并延伸核心单元的行或列的整个长度。
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2.发明授权Method for providing contact separation in silicided devices using false gate 失效使用假门在硅化器件中提供接触分离的方法
公开(公告)号：US4753897A
公开(公告)日：1988-06-28
申请号：US839848
申请日：1986-03-14
IPC分类号： H01L21/768 , H01L21/28 , H01L21/3213 , H01L21/336 , H01L21/60 , H01L29/78 , H01L21/283
CPC分类号： H01L21/76897 , H01L29/66575 , H01L2924/0002 , Y10S148/019 , Y10S148/147
摘要： A method for providing platinum or tungsten silicide contacts to source, drain, gate and tub regions of a dielectrically isolated MOSFET is described. A "false" (dummy) gate is used to provide automatic self-aligned separation of the source-drain contact and the tub contact. An intermetallic forming material (refractory metal) is uniformly coated over the doped substrate on which the gate and false gate region have been formed in a spaced-apart fashion. Upon heating the intermetallic forming layer reacts with the substrate and the polysilicon gates to form intermetallic regions. The remaining portion of the intermetallic forming layer is differentially etched away from the dielectric isolation walls and the sidewall oxides on either side of the gate and false gate. Alternatively, selective deposition may be used to avoid deposition on the dielectric regions. The false gate extends laterally across the isolation tub. This procedure separates the device contacts from the tub contact without the use of separate masking layers. A more compact structure is obtained.
摘要翻译： 描述了用于向介电隔离MOSFET的源极，漏极，栅极和阱区提供铂或硅化钨接触的方法。 使用“假”（虚拟）门来提供源极 - 漏极触点和水桶触点的自动自对准分离。 金属间形成材料（难熔金属）均匀地涂覆在掺杂的衬底上，栅极和假栅极区域已经以间隔开的方式形成在其上。 在加热时，金属间形成层与基板和多晶硅栅极反应以形成金属间区域。 金属间形成层的剩余部分与栅极和假栅极两侧的电介质隔离壁和侧壁氧化物差异地蚀刻。 或者，可以使用选择性沉积来避免沉积在电介质区域上。 假门横向延伸穿过隔离桶。 该过程将设备触点与桶接触分开，而不使用单独的掩蔽层。 获得更紧凑的结构。
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3.发明授权
公开(公告)号：US4908688A
公开(公告)日：1990-03-13
申请号：US132822
申请日：1987-12-14
IPC分类号： H01L21/336 , H01L21/60
CPC分类号： H01L21/76897 , H01L29/66575
摘要： A means and method for providing platinum or tungsten silicide contacts to source, drain, gate and tub regions of a dielectrically isolated MOSFET is described. A "false" gate is used to provide automatic self-aligned separation of the source-drain contact and the tub contact. An intermetallic forming material is uniformly coated over the doped substrate on which the gate and false gate region have been formed in a spaced-apart fashion. Upon heating the intermetallic forming layer reacts with the substrate and the polysilicon gates to form intermetallic regions. The remaining portion of the intermetallic forming layer is differentially etched away from the dielectric isolation walls and the sidewall oxides on either side of the gate and false gate. Alernatively, selective deposition may be used to avoid deposition on the dielectric regions. The false gate extends laterally across the isolation tub. This procedure separates the device contacts from the tub contact without the use of separate masking layers. A more compact structure is obtained.
摘要翻译： 描述了用于向介电隔离MOSFET的源极，漏极，栅极和阱区提供铂或钨硅化物触点的方法和方法。 使用“假”门来提供源极 - 漏极接触和浴缸触点的自动自对准分离。 金属间形成材料均匀地涂覆在已经以间隔开的方式形成栅极和假栅极区域的掺杂衬底上。 在加热时，金属间形成层与基板和多晶硅栅极反应以形成金属间区域。 金属间形成层的剩余部分与栅极和假栅极两侧的电介质隔离壁和侧壁氧化物差异地蚀刻。 同时，可以使用选择性沉积来避免沉积在电介质区域上。 假门横向延伸穿过隔离桶。 该过程将设备触点与桶接触分开，而不使用单独的掩蔽层。 获得更紧凑的结构。
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