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1.发明授权Method and apparatus for allowing communication in an isochronous traffic of asynchronous transfer mode (ATM) cells in a ring network 失效允许在环形网络中的异步传输模式（ATM）小区的等时业务中的通信的方法和装置
公开(公告)号：US6104714A
公开(公告)日：2000-08-15
申请号：US932547
申请日：1997-09-17
CPC分类号： H04Q11/0478 , H04L2012/5612
摘要： A method and apparatus for an isochronous traffic of Asynchronous Transfer Mode (ATM) cells in a ring network having at least two stations (101,102) and a ring server (001). The communication within the ring is based on specific isochronous control and data cells. The control cell contains a cell header, sequence number, type of command and parameter fields. The data cell contains a header and a payload divided into N m-bit slots. The isochronous data cells are shared by a plurality of stations on the ring by allocating corresponding slotlist whose identification is carried in the parameter field. Furthermore, the server provides for each station's communication link a transmit identifier in the header associated to a reference in a list of allocated slots for transmission and a receive identifier associated to a reference in a list of allocated slots for reception. The implementation of two pairs of registers whose bits correspond to each byte of the isochronous data cell enables processing in real time transmission and reception of the isochronous data cells and to concatenate the bytes to be stored in a memory and to transmit transparently unmodified or substituted bytes on the ring.
摘要翻译： 一种用于具有至少两个站（101,102）和环形服务器（001）的环形网络中的异步传输模式（ATM）小区的等时业务的方法和装置。 环内的通信基于特定的等时控制和数据信元。 控制单元包含单元头，序列号，命令类型和参数字段。 数据信元包含标题和分为N个m位时隙的净荷。 同步数据信元由环路上的多个站共享，分配对应的在列表中携带标识的槽位列表。 此外，服务器为每个站的通信链路提供与在分配的用于传输的时隙的列表中的参考相关联的头部中的发送标识符以及与用于接收的所分配的时隙的列表中的参考相关联的接收标识符。 位对应于同步数据单元的每个字节的两对寄存器的实现使得能够实时处理同步数据单元的发送和接收，并且将要存储在存储器中的字节连接并且透明地未修改或替换的字节 在戒指上
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公开(公告)号：US07751312B2
公开(公告)日：2010-07-06
申请号：US10860293
申请日：2004-06-03
申请人： Alain Benayoun , Patrick Michel , Gilles Toubol
发明人： Alain Benayoun , Patrick Michel , Gilles Toubol
IPC分类号： G01R31/08
CPC分类号： H04L49/552 , H04L49/1523
摘要： The disclosed invention relates to a re-synchronization system that operates in a switching arrangement receiving a plurality of incoming data packets. The switching arrangement is made of an active switch card that transmits the incoming data packets and a backup switch card that may be re-activated by an operator after replacement. The re-synchronization system is implemented in each switch card. When the backup switch card is re-activated, both switch cards receive the incoming data packets and the system of the invention allows to re-synchronized both switch cards by controlling the transmission of the incoming data packets out of each switch card until the same data packets are transmitted. The re-synchronization system further comprise storage for storing the incoming data packets and detector for detecting a re-synchronization information among the incoming data packets.
摘要翻译： 所公开的本发明涉及一种在接收多个输入数据分组的交换机构中操作的再同步系统。 切换装置由传送数据包的主动交换卡和备用交换机卡组成，备用交换机卡可以由操作员在更换后重新激活。 在每个交换机卡中实现重新同步系统。 当备用交换卡被重新启动时，两个交换卡都接收输入的数据包，并且本发明的系统允许通过控制每个交换机卡中的输入数据分组的传输来重新同步两个交换机卡，直到相同的数据 数据包被传输。 重新同步系统还包括用于存储输入数据分组的存储器和用于检测输入数据分组之间的重新同步信息的检测器。
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公开(公告)号：US20080196032A1
公开(公告)日：2008-08-14
申请号：US12109001
申请日：2008-04-24
IPC分类号： G06F9/46
CPC分类号： G06F9/30101 , G06F9/3836
摘要： A hardware device for processing the tasks of an algorithm of the type having a number of processes the execution of some of which depend on binary decisions has a plurality of task units (10, 12, 14), each of which are associated with a task defined as being either one process or one decision or one process together with a following decision. A task interconnection logic block (16) is connected to each task unit for communicating actions from a source task unit to a destination task unit. Each task unit includes a processor (18) for processing the steps of the associated task when a received action requests such a processing. A status manager (20) handles actions coming from other task units and builds actions to be sent to other task units
摘要翻译： 一种硬件设备，用于处理具有多个进程数量的处理类型的算法的任务取决于二进制决定的任务具有多个任务单元（10,12,14），每个任务单元与任务相关联 定义为一个过程或一个决策或一个过程以及以下决定。 任务互连逻辑块（16）连接到每个任务单元，用于将来自源任务单元的操作传送到目的地任务单元。 每个任务单元包括处理器（18），用于在接收的动作请求这样的处理时处理相关任务的步骤。 状态管理器（20）处理来自其他任务单元的动作，并构建要发送到其他任务单元的动作
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公开(公告)号：US07203735B1
公开(公告)日：2007-04-10
申请号：US09659649
申请日：2000-09-12
IPC分类号： G06F15/16
CPC分类号： G06F17/30194
摘要： In a remote computer, a method for providing a file comprises the steps of receiving a request for this file, identifying this file as being stored in a distant server, requesting the distance server to send the file, identifying this file as being used, and forwarding this file. Further, in a local server, a method for transferring a file from a home server comprises the steps of receiving a request for this file, this request comprising the home server identification, checking that this file is not locally stored, requesting this file to the home server, identifying the file as being locally used, and forwarding this file.
摘要翻译： 在远程计算机中，用于提供文件的方法包括以下步骤：接收对该文件的请求，将该文件识别为存储在远程服务器中，请求距离服务器发送文件，将该文件识别为使用，以及 转发此文件。 此外，在本地服务器中，用于从家庭服务器传送文件的方法包括以下步骤：接收对该文件的请求，该请求包括家庭服务器标识，检查该文件不是本地存储的，请求该文件到 家庭服务器，将文件标识为本地使用，并转发此文件。
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公开(公告)号：US07085802B1
公开(公告)日：2006-08-01
申请号：US09680798
申请日：2000-10-06
IPC分类号： G06F13/00
CPC分类号： G06F13/4059
摘要： According to the invention, a device for transferring data between two workstations connected to a network is provided. This device comprises means for distributing data among a plurality of links of the network. Preferentially, the device comprises a dual-port memory for storing the data. In a preferred embodiment, the device further comprises a high speed interface for transmitting data from a workstation to the memory, associated with each link, a low speed interface for transmitting a part of the data from the memory to this link, and a controller for monitoring the data flow between the workstation and the plurality of links, by controlling the memory and the interfaces.
摘要翻译： 根据本发明，提供了一种用于在连接到网络的两个工作站之间传送数据的设备。 该设备包括用于在网络的多个链路之间分发数据的装置。 优选地，该设备包括用于存储数据的双端口存储器。 在优选实施例中，该设备还包括用于将数据从工作站发送到与每个链路相关联的存储器的高速接口，用于将数据的一部分从存储器传输到该链路的低速接口，以及用于 通过控制存储器和接口来监视工作站和多个链路之间的数据流。
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公开(公告)号：US07006498B2
公开(公告)日：2006-02-28
申请号：US09920683
申请日：2001-08-02
申请人： Alain Benayoun , Patrick Michel , Gilles Toubol
发明人： Alain Benayoun , Patrick Michel , Gilles Toubol
CPC分类号： H04L12/4608
摘要： An improved data transmission system including multiple local area networks (LANs) coupled by a hub that further includes multiple LAN adapters coupled to the LANs, and an asynchronous transfer mode (ATM) crossbar switch coupling all LAN adapters. LAN data frames are converted into concatenated slots of an identical size and transmitted through the ATM crossbar switch. At least the requesting LAN adapter coupled to the LAN to transmit LAN data frame includes a serial communication controller (SCC) that converts a received LAN data frame into serial data. The SCC also includes a means for converting serial data to LAN data frames.
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公开(公告)号：US06823348B2
公开(公告)日：2004-11-23
申请号：US09493242
申请日：2000-01-28
IPC分类号： G06F1730
CPC分类号： G06F17/30067 , Y10S707/99953 , Y10S707/99954
摘要： A file manager (and method) provided for locating a file identified by a path referring to a logical unit and an identifier, includes a table associating the file with a priority list of physical units. The file manager can be incorporated into the controller of peripheral devices in a computer system or an operating system of the computer system.
摘要翻译： 提供用于定位由参考逻辑单元和标识符的路径识别的文件的文件管理器（和方法）包括将文件与物理单元的优先级列表相关联的表格。 文件管理器可以并入到计算机系统或计算机系统的操作系统中的外围设备的控制器中。
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8.发明授权Method and apparatus for processing FISU frames according to the Signalling System 7 protocol 失效根据信令系统7协议处理FISU帧的方法和装置公开(公告)号：US06219416B1
公开(公告)日：2001-04-17
申请号：US08807491
申请日：1997-02-27
IPC分类号： H04M1500
CPC分类号： H04Q3/0025 , H04Q2213/13003 , H04Q2213/13103 , H04Q2213/13174 , H04Q2213/13176 , H04Q2213/13216 , H04Q2213/13305 , H04Q2213/1332 , H04Q2213/13322
摘要： A FISU frame handler which is connected between an adapter and a SS7 low speed network. For each FISU frames transmitted or received in the adapter, an interrupt is generated to a processor located in the adapter. In order to diminish the number of processor interruptions, the FISU frames are externally processed by the FISU frame handler by discarding repeated FISU frames transmitted from the network so as to generate idle state signals to the adapter and by converting idle state signals received from the adapter into repetitive FISU frames to transmit them to the network without interrupting the processor. In order to perform both functions, the FISU frame handler comprises two dedicated hardware units which operate according to specific methods.
摘要翻译： 连接在适配器和SS7低速网络之间的FISU帧处理器。 对于在适配器中发送或接收的每个FISU帧，将向位于适配器中的处理器生成中断。 为了减少处理器中断次数，FISU帧由FISU帧处理器通过丢弃从网络发送的重复的FISU帧来进行外部处理，以便向适配器产生空闲状态信号，并通过转换从适配器接收的空闲状态信号 重复的FISU帧将其发送到网络而不中断处理器。 为了执行这两个功能，FISU帧处理器包括根据特定方法操作的两个专用硬件单元。
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公开(公告)号：US06999994B1
公开(公告)日：2006-02-14
申请号：US09606899
申请日：2000-06-29
CPC分类号： G06F9/30101 , G06F9/3836
摘要： A hardware device for processing the tasks of an algorithm of the type having a number of processes the execution of some of which depend on binary decisions has a plurality of task units (10, 12, 14), each of which are associated with a task defined as being either one process or one decision or one process together with a following decision. A task interconnection logic block (16) is connected to each task unit for communicating actions from a source task unit to a destination task unit. Each task unit includes a processor (18) for processing the steps of the associated task when a received action requests such a processing. A status manager (20) handles actions coming from other task units and builds actions to be sent to other task units.
摘要翻译： 一种硬件设备，用于处理具有多个进程数量的处理类型的算法的任务取决于二进制决定的任务具有多个任务单元（10,12,14），每个任务单元与任务相关联 定义为一个过程或一个决策或一个过程以及以下决定。 任务互连逻辑块（16）连接到每个任务单元，用于将来自源任务单元的操作传送到目的地任务单元。 每个任务单元包括处理器（18），用于在接收的动作请求这样的处理时处理相关任务的步骤。 状态管理器（20）处理来自其他任务单元的动作，并构建要发送到其他任务单元的动作。
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10.发明授权公开(公告)号：US06961337B2
公开(公告)日：2005-11-01
申请号：US09753921
申请日：2001-01-03
IPC分类号： H04L12/701 , H04L12/741 , H04L12/773 , H04L12/28
CPC分类号： H04L45/60 , H04L45/00 , H04L45/54 , Y10S707/99933
摘要： A system and method for performing interleaved packet processing. A packet includes a source address bit pattern and a destination address bit pattern that are processed by a task processor in accordance with a data tree. A first bank of registers is utilized to load an instruction to be executed by the task processor at nodes of the data tree in accordance with the source address bit pattern. A second bank of registers is utilized for loading an instruction to be executed by the task processor at nodes of the data tree in accordance with the destination address bit pattern. A task scheduler enables the first bank of registers to transfer an instruction loaded therein for processing by the task processor only during even time cycles and for enabling the second bank of registers to transfer an instruction loaded therein for processing by the task processor only during odd time cycles.
摘要翻译： 一种用于执行交织分组处理的系统和方法。 分组包括根据数据树由任务处理器处理的源地址位模式和目的地地址位模式。 根据源地址位模式，第一组寄存器被用来加载任务处理器在数据树的节点执行的指令。 第二组寄存器用于根据目的地地址位模式将在任务处理器执行的指令加载到数据树的节点处。 任务调度器使得第一组寄存器仅在偶数时间周期期间传送加载在其中以供任务处理器处理的指令，并且仅允许第二组寄存器在奇数时间内传送其中加载的指令以供任务处理器处理 周期。
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