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公开(公告)号：US20110121295A1
公开(公告)日：2011-05-26
申请号：US13019643
申请日：2011-02-02
IPC分类号： H01L23/488
CPC分类号： H01L24/13 , H01L22/34 , H01L24/11 , H01L2224/0392 , H01L2224/0401 , H01L2224/05567 , H01L2224/13007 , H01L2224/13099 , H01L2224/131 , H01L2924/0001 , H01L2924/0002 , H01L2924/01006 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2224/05552
摘要： A semiconductor device includes a substrate having a first conductive layer disposed on a top surface of the substrate. A first insulation layer is formed over the substrate and contacts a sidewall of the first conductive layer. A second conductive layer is formed over the first insulation layer. The second conductive layer includes a first portion disposed over the first conductive layer and a second portion that extends beyond an end of the first conductive layer. A second insulation layer is formed over the second conductive layer. A first opening in the second insulation layer exposes the first portion of the second conductive layer. A second opening in the second insulation layer away from the first opening exposes the second portion of the second conductive layer. The second insulation layer is maintained around the first opening. A conductive bump is formed over the first portion of the second conductive layer.
摘要翻译： 半导体器件包括具有设置在衬底顶表面上的第一导电层的衬底。 第一绝缘层形成在衬底上并与第一导电层的侧壁接触。 在第一绝缘层上形成第二导电层。 第二导电层包括设置在第一导电层上的第一部分和延伸超出第一导电层的端部的第二部分。 在第二导电层上形成第二绝缘层。 第二绝缘层中的第一开口露出第二导电层的第一部分。 远离第一开口的第二绝缘层中的第二开口暴露第二导电层的第二部分。 第二绝缘层保持在第一开口周围。 导电凸块形成在第二导电层的第一部分之上。
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公开(公告)号：US08203145B2
公开(公告)日：2012-06-19
申请号：US13019643
申请日：2011-02-02
IPC分类号： H01L23/488
CPC分类号： H01L24/13 , H01L22/34 , H01L24/11 , H01L2224/0392 , H01L2224/0401 , H01L2224/05567 , H01L2224/13007 , H01L2224/13099 , H01L2224/131 , H01L2924/0001 , H01L2924/0002 , H01L2924/01006 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2224/05552
摘要： A semiconductor device includes a substrate having a first conductive layer disposed on a top surface of the substrate. A first insulation layer is formed over the substrate and contacts a sidewall of the first conductive layer. A second conductive layer is formed over the first insulation layer. The second conductive layer includes a first portion disposed over the first conductive layer and a second portion that extends beyond an end of the first conductive layer. A second insulation layer is formed over the second conductive layer. A first opening in the second insulation layer exposes the first portion of the second conductive layer. A second opening in the second insulation layer away from the first opening exposes the second portion of the second conductive layer. The second insulation layer is maintained around the first opening. A conductive bump is formed over the first portion of the second conductive layer.
摘要翻译： 半导体器件包括具有设置在衬底顶表面上的第一导电层的衬底。 第一绝缘层形成在衬底上并与第一导电层的侧壁接触。 在第一绝缘层上形成第二导电层。 第二导电层包括设置在第一导电层上的第一部分和延伸超出第一导电层的端部的第二部分。 在第二导电层上形成第二绝缘层。 第二绝缘层中的第一开口露出第二导电层的第一部分。 远离第一开口的第二绝缘层中的第二开口暴露第二导电层的第二部分。 第二绝缘层保持在第一开口周围。 导电凸块形成在第二导电层的第一部分之上。
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公开(公告)号：US07901956B2
公开(公告)日：2011-03-08
申请号：US11464726
申请日：2006-08-15
CPC分类号： H01L24/13 , H01L22/34 , H01L24/11 , H01L2224/0392 , H01L2224/0401 , H01L2224/05567 , H01L2224/13007 , H01L2224/13099 , H01L2224/131 , H01L2924/0001 , H01L2924/0002 , H01L2924/01006 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2224/05552
摘要： A semiconductor package includes a substrate having a bond pad disposed on a top surface of the substrate. A first passivation layer is formed over the substrate and bond pad. The first passivation layer has an opening to expose the bond pad. An under bump metallurgy is formed over the first passivation layer. An end of the under bump metallurgy extends beyond an end of the bond pad. A second passivation layer is formed over the under bump metallurgy. The second passivation layer has a first opening to expose a first surface of the under bump metallurgy, and a second opening which is etched to expose a second surface of the under bump metallurgy. A solder ball is attached to the first surface of the under bump metallurgy to provide electrical connectivity. The second opening in the second passivation layer receives a probe needle to test the semiconductor device.
摘要翻译： 半导体封装包括具有设置在基板的顶表面上的接合焊盘的基板。 在衬底和接合焊盘上形成第一钝化层。 第一钝化层具有露出接合焊盘的开口。 在第一钝化层上形成凸块下金属。 凸块下的冶金结束延伸超过接合焊盘的端部。 在凸块下金属上形成第二钝化层。 第二钝化层具有第一开口以暴露凸块下金属冶金的第一表面，以及第二开口，其蚀刻以暴露凸块下金属的第二表面。 焊球附着在凸块下金属冶金的第一表面以提供电连接。 第二钝化层中的第二开口接收探针以测试半导体器件。
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公开(公告)号：US20080042275A1
公开(公告)日：2008-02-21
申请号：US11464726
申请日：2006-08-15
CPC分类号： H01L24/13 , H01L22/34 , H01L24/11 , H01L2224/0392 , H01L2224/0401 , H01L2224/05567 , H01L2224/13007 , H01L2224/13099 , H01L2224/131 , H01L2924/0001 , H01L2924/0002 , H01L2924/01006 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2224/05552
摘要： A semiconductor package includes a substrate having a bond pad disposed on a top surface of the substrate. A first passivation layer is formed over the substrate and bond pad. The first passivation layer has an opening to expose the bond pad. An under bump metallurgy is formed over the first passivation layer. An end of the under bump metallurgy extends beyond an end of the bond pad. A second passivation layer is formed over the under bump metallurgy. The second passivation layer has a first opening to expose a first surface of the under bump metallurgy, and a second opening which is etched to expose a second surface of the under bump metallurgy. A solder ball is attached to the first surface of the under bump metallurgy to provide electrical connectivity. The second opening in the second passivation layer receives a probe needle to test the semiconductor device.
摘要翻译： 半导体封装包括具有设置在基板的顶表面上的接合焊盘的基板。 在衬底和接合焊盘上形成第一钝化层。 第一钝化层具有露出接合焊盘的开口。 在第一钝化层上形成凸块下金属。 凸块下的冶金结束延伸超过接合焊盘的端部。 在凸块下金属上形成第二钝化层。 第二钝化层具有第一开口以暴露凸块下金属冶金的第一表面，以及第二开口，其蚀刻以暴露凸块下金属的第二表面。 焊球附着在凸块下金属冶金的第一表面以提供电连接。 第二钝化层中的第二开口接收探针以测试半导体器件。
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