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公开(公告)号：US08863065B1
公开(公告)日：2014-10-14
申请号：US12775363
申请日：2010-05-06
IPC分类号： G06F17/50
CPC分类号： H03K19/17796 , H01L25/0657 , H01L25/18 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A programmable device system includes one or more network-on-chip (NoC) die layers vertically connected to one or more programmable chip dice layers. The NoC die layer includes interconnects, a bus or non-blocking switches, and optionally memory blocks and direct memory access engines. The NoC die layer improves on-chip communications by providing fast and direct interconnection circuitry between various parts of the programmable chip die.
摘要翻译： 可编程器件系统包括垂直连接到一个或多个可编程芯片芯片层的一个或多个芯片上芯片（NoC）裸片层。 NoC模块层包括互连，总线或非阻塞开关，以及可选的存储器块和直接存储器访问引擎。 NoC裸片层通过在可编程芯片裸片的各个部分之间提供快速和直接的互连电路来改善片上通信。
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公开(公告)号：US07701252B1
公开(公告)日：2010-04-20
申请号：US12074467
申请日：2008-03-03
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H03K19/17796 , H01L25/0657 , H01L25/18 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A programmable device system includes one or more network-on-chip (NoC) die layers vertically connected to one or more programmable chip dice layers. The NoC die layer includes interconnects, a bus or non-blocking switches, and optionally memory blocks and direct memory access engines. The NoC die layer improves on-chip communications by providing fast and direct interconnection circuitry between various parts of the programmable chip die.
摘要翻译： 可编程器件系统包括垂直连接到一个或多个可编程芯片芯片层的一个或多个芯片上芯片（NoC）裸片层。 NoC模块层包括互连，总线或非阻塞开关，以及可选的存储器块和直接存储器访问引擎。 NoC裸片层通过在可编程芯片裸片的各个部分之间提供快速和直接的互连电路来改善片上通信。
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公开(公告)号：US08719753B1
公开(公告)日：2014-05-06
申请号：US12703681
申请日：2010-02-10
IPC分类号： G06F17/50
CPC分类号： H03K19/17796 , H01L25/0657 , H01L25/18 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A programmable device system includes one or more network-on-chip (NoC) die layers vertically connected to one or more programmable chip dice layers. The NoC die layer includes interconnects, a bus or non-blocking switches, and optionally memory blocks and direct memory access engines. The NoC die layer improves on-chip communications by providing fast and direct interconnection circuitry between various parts of the programmable chip die.
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公开(公告)号：US20090271465A1
公开(公告)日：2009-10-29
申请号：US12111156
申请日：2008-04-28
IPC分类号： G06F7/485
摘要： Hybrid adder circuitry is provided for integrated circuits such as programmable integrated circuits. The hybrid adder may combine the capabilities of multiple adder architectures. Hybrid adders may include carry select and carry ripple adder circuits. The adder circuits may be combined using a carry look-ahead architecture. Adder functionality may be implemented using the resources of logic regions on the programmable integrated circuits. Each logic region may include combinatorial logic such as look-up table logic and register circuitry. The hybrid adder circuitry may receive input words to be added from the combinatorial circuitry and may produce corresponding arithmetic sum output signals to the register circuitry.
摘要翻译： 为诸如可编程集成电路的集成电路提供混合加法器电路。 混合加法器可以组合多个加法器架构的能力。 混合加法器可以包括进位选择和进位纹波加法器电路。 加法器电路可以使用携带查找结构来组合。 可以使用可编程集成电路上的逻辑区域的资源来实现加法器功能。 每个逻辑区域可以包括诸如查找表逻辑和寄存器电路的组合逻辑。 混合加法器电路可以从组合电路接收要添加的输入字，并且可以向寄存器电路产生相应的算术和输出信号。
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5.发明授权公开(公告)号：US08161469B1
公开(公告)日：2012-04-17
申请号：US11302568
申请日：2005-12-13
IPC分类号： G06F9/45
CPC分类号： G06F17/504 , G06F17/5054
摘要： Compiled configuration files for different programmable logic devices that are intended to be functionally equivalent may be compared using multiple different comparisons to assure functional equivalence. The different comparisons include a fitter or resource report comparison, an engineering bit settings report that compares vectors of bits that represent the settings of hard logic blocks, and comparisons based on location, connectivity and functionality. These comparisons are particularly well-suited for determining equivalence between different models of programmable logic devices, or even different types of devices such as field-programmable gate arrays as compared to mask-programmable logic devices.
摘要翻译： 可以使用多个不同的比较来比较旨在功能等同的不同可编程逻辑器件的编译配置文件，以确保功能等同性。 不同的比较包括装配者或资源报告比较，工程位设置报告，比较表示硬逻辑块设置的位的向量，以及基于位置，连接和功能的比较。 与掩模可编程逻辑器件相比，这些比较特别适合于确定不同型号的可编程逻辑器件或甚至不同类型的器件（例如现场可编程门阵列）之间的等效性。
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公开(公告)号：US08521801B2
公开(公告)日：2013-08-27
申请号：US12111156
申请日：2008-04-28
IPC分类号： G06F7/50
摘要： Hybrid adder circuitry is provided for integrated circuits such as programmable integrated circuits. The hybrid adder may combine the capabilities of multiple adder architectures. Hybrid adders may include carry select and carry ripple adder circuits. The adder circuits may be combined using a carry look-ahead architecture. Adder functionality may be implemented using the resources of logic regions on the programmable integrated circuits. Each logic region may include combinatorial logic such as look-up table logic and register circuitry. The hybrid adder circuitry may receive input words to be added from the combinatorial circuitry and may produce corresponding arithmetic sum output signals to the register circuitry.
摘要翻译： 为诸如可编程集成电路的集成电路提供混合加法器电路。 混合加法器可以组合多个加法器架构的能力。 混合加法器可以包括进位选择和进位纹波加法器电路。 加法器电路可以使用携带查找结构来组合。 可以使用可编程集成电路上的逻辑区域的资源来实现加法器功能。 每个逻辑区域可以包括诸如查找表逻辑和寄存器电路的组合逻辑。 混合加法器电路可以从组合电路接收要添加的输入字，并且可以向寄存器电路产生相应的算术和输出信号。
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7.发明授权公开(公告)号：US07804325B1
公开(公告)日：2010-09-28
申请号：US12148877
申请日：2008-04-22
IPC分类号： H03K19/173
CPC分类号： H03K19/177
摘要： To improve interfacing between a block of dedicated function circuitry and blocks of more general purpose circuitry on an integrated circuit (“IC”), signals that are to be output by the dedicated function block are routed internally in that block so that they go into interconnection circuitry on the IC for more efficient application by that interconnection circuitry to the general purpose circuitry. Some of this routing internal to the dedicated function block may be controllably variable. The routing internal to the dedicated function block may also be arranged to take advantage of “sneak” connections that may exist between the dedicated function block and the general purpose blocks.
摘要翻译： 为了改善专用功能电路块与集成电路（“IC”）上更通用电路的块之间的接口，由专用功能块输出的信号在该块内部被路由到它们进入互连 IC上的电路，用于将该互连电路更有效地应用于通用电路。 专用功能块内部的一些路由可能是可控的。 专用功能块内部的路由也可以被布置为利用可能存在于专用功能块和通用块之间的“潜行”连接。
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