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1.发明授权Method for power routing and distribution in an integrated circuit with multiple interconnect layers 有权具有多个互连层的集成电路中的电力布线和分配方法公开(公告)号：US06581201B2
公开(公告)日：2003-06-17
申请号：US09969378
申请日：2001-10-02
IPC分类号： G06F1750
CPC分类号： G06F17/5068 , G06F17/5077 , G06F2217/78 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit 210 has a power grid formed from a first set of power buses 201a and 202a on a metal interconnect level M1, a second set of power buses 203a and 204a on interconnect level M4, and a third set of power buses 205a and 206a on interconnect level M5. The set of power buses on level M4 are oriented in the same direction as the set of power buses on level M1, and both sets of buses are located coincidentally. A high power logic cell 220 is pre-defined with a set of M1-M4 power vias 221 and 222 so that logic cell 220 can be positioned in a horizontal row unconstrained by pre-positioned M1-M4 power vias. Dummy cell 230 with M1-M4 power vias is positioned as needed so as not to exceed a maximum strapping distance D1. A maximum value for distance D1 is selected based on dynamic power requirements of nearby logic cells 250a-n as determined by simulation. A method for designing and fabricating integrated circuit 210 is described.
摘要翻译： 集成电路210具有由金属互连级M1上的第一组电源总线201a和202a形成的电网，以及互连级M4上的第二组电源总线203a和204a以及第三组电源总线205a和206a 在互连级别M5上。 M4级的电力总线集合方向与M1级的电力总线相同，两组总线同时定位。 高功率逻辑单元220用一组M1-M4电源通孔221和222预定义，使得逻辑单元220可以被定位在不受预定义的M1-M4电源通孔约束的水平行中。 具有M1-M4电源通孔的假电池230根据需要定位，以便不超过最大捆扎距离D1。 基于通过仿真确定的附近的逻辑单元250a-n的动态功率要求来选择距离D1的最大值。 描述了集成电路210的设计和制造方法。
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2.发明授权Method for power routing and distribution in an integrated circuit with multiple interconnect layers 有权具有多个互连层的集成电路中的电力布线和分配方法公开(公告)号：US06308307B1
公开(公告)日：2001-10-23
申请号：US09240126
申请日：1999-01-29
IPC分类号： G06F1750
CPC分类号： G06F17/5068 , G06F17/5077 , G06F2217/78 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit 210 has a power grid formed from a first set of power buses 201a and 202a on a metal interconnect level M1, a second set of power buses 203a and 204a on interconnect level M4, and a third set of power buses 205a and 206a on inter-connect level M5. The set of power buses on level M4 are oriented in the same direction as the set of power buses on level M1, and both sets of buses are located coincidentally. A high power logic cell 220 is pre-defined with a set of M1-M4 power vias 221 and 222 so that logic cell 220 can be positioned in a horizontal row unconstrained by pre-positioned M1-M4 power vias. Dummy cell 230 with M1-M4 power vias is positioned as needed so as not to exceed a maximum strapping distance D1. A maximum value for distance D1 is selected based on dynamic power requirements of nearby logic cells 250a-n as determined by simulation. A method for designing and fabricating integrated circuit 210 is described.
摘要翻译： 集成电路210具有由金属互连级M1上的第一组电源总线201a和202a形成的电网，以及互连级M4上的第二组电源总线203a和204a以及第三组电源总线205a和206a 在连接间级别M5上。 M4级的电力总线集合方向与M1级的电力总线相同，两组总线同时定位。 高功率逻辑单元220用一组M1-M4电源通孔221和222预定义，使得逻辑单元220可以被定位在不受预定义的M1-M4电源通孔约束的水平行中。 具有M1-M4电源通孔的假电池230根据需要定位，以便不超过最大捆扎距离D1。 基于通过仿真确定的附近的逻辑单元250a-n的动态功率要求来选择距离D1的最大值。 描述了集成电路210的设计和制造方法。
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3.发明授权Method and apparatus for altering timing relationships of non-overlapping clock signals in a microprocessor 有权用于改变微处理器中非重叠时钟信号的定时关系的方法和装置公开(公告)号：US06381704B1
公开(公告)日：2002-04-30
申请号：US09240271
申请日：1999-01-29
申请人： Francisco A. Cano , Rajib Nag , Robert E. Farrell
发明人： Francisco A. Cano , Rajib Nag , Robert E. Farrell
IPC分类号： G06F104
CPC分类号： G01R31/318552
摘要： A clock generation circuit 122 with a selectable non-overlap time period is described for use on an integrated circuit. A master clock signal M which has a latching edge is formed in response to a reference clock signal fclk. A slave clock signal S which has a driving edge is also formed in response to the reference clock signal. The driving edge of slave clock S is delayed by a non-overlap feedback path 504 so that the driving edge is delayed by the non-overlap time period after the latching edge of master clock M. The value of the non-overlap time period is selected by switching delay circuitry 531 in or out of the non-overlap feedback path on signal line 504. A control signal STRSTST is set high or low to select the value of the non-overlap time period. A sense circuit 561 or a scan latch 562 also can select the non-overlap time period.
摘要翻译： 描述了在集成电路上使用具有可选非重叠时间段的时钟产生电路122。 响应于参考时钟信号fclk形成具有锁存边缘的主时钟信号M. 具有驱动边缘的从时钟信号S也响应于参考时钟信号而形成。 从时钟S的驱动边缘被非重叠反馈路径504延迟，使得驱动边缘被延迟主时钟M的锁存边沿之后的非重叠时间段。非重叠时间段的值是 通过将延迟电路531切换到信号线504上的非重叠反馈路径中来选择。控制信号STRSTST被设置为高或低以选择非重叠时间段的值。 感测电路561或扫描锁存器562也可以选择非重叠时间段。
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公开(公告)号：US06363516B1
公开(公告)日：2002-03-26
申请号：US09438808
申请日：1999-11-12
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： In deep submicron technologies, coupling capacitance significantly dominates the total parasitic capacitance. This causes crosstalk noise to be induced on quiescent signals which could lead to catastrophic failures. A method is provided for extracting parasitic data in a hierarchical manner from a trial layout of the integrated circuit. Intracellular parasitic data representative each cell type used in the integrated circuit is extracted only once, regardless of the number of times the cell is instantiated in the integrated circuit. For each instance of each cell, a portion of intercell signal lines that are routed over that instance of the cell are cut out in cookie cutter fashion by specifying an area in the trial layout corresponding to the instance of the cell such that the portion of intercell signal lines within the area can be processed apart from the remaining portion of the intercell signal lines. Each cutout portion of the over the cell routing (OCR) is combined with the respective cell instance and OCR parasitic data is extracted with reference to the respective cell. For each cell instance, the intracellular parasitic data derived once for the cell is combined with the OCR parasitic information derived for that cell instance in order to form a coupled simulation model.
摘要翻译： 在深亚微米技术中，耦合电容显着支配总寄生电容。 这会导致串扰噪声在静态信号上产生，这可能导致灾难性故障。 提供了一种从集成电路的试用布局以分层方式提取寄生数据的方法。 代表集成电路中使用的每种单元类型的细胞内寄生数据仅提取一次，而与集成电路中的单元被实例化的次数无关。 对于每个单元的每个实例，通过指定与该单元的实例相对应的试用布局中的区域，以cookie切割方式切出在该单元的该实例上路由的一部分小区间信号线，使得该小区的该部分 区域内的信号线可以与单元间信号线的剩余部分分开处理。 小区路由（OCR）上的每个切出部分与相应的小区实例组合，并且参考相应小区提取OCR寄生数据。 对于每个细胞实例，将针对细胞一次导出的细胞内寄生数据与为该细胞实例导出的OCR寄生信息组合以形成耦合模拟模型。
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5.发明授权Method for analyzing circuit delays caused by capacitive coupling in digital circuits 有权分析数字电路中电容耦合引起的电路延迟的方法公开(公告)号：US06253359B1
公开(公告)日：2001-06-26
申请号：US09240993
申请日：1999-01-29
IPC分类号： G06F1750
CPC分类号： G06F17/5022 , G06F17/5068 , Y02T10/82
摘要： A method for designing and fabricating an integrated circuit is described. An increase or a decrease in a total propagation delay time 311 of a signal on a victim net 203 is accurately modeled using a modified decoupled simulation model 300. Victim net 203 is modeled as a distributed capacitor 320a-c that has a total value equal to Cgnd+2*K*Ccoup. A match propagation delay time which includes a variation in propagation delay caused by signal coupling from aggressor nets located adjacent to the victim net is determined by simulating a representative circuit using a coupled distributed load simulation model to accurately determine the match propagation delay time. K is determined using an equation in which K=1+(match delay−unmodified delay)/(2*R*Ccoup). R is the effective drive resistance of a buffer which drives the victim net and associated signal trace resistance.
摘要翻译： 描述了一种用于设计和制造集成电路的方法。 牺牲网203上的信号的总传播延迟时间311的增加或减少使用修改的解耦仿真模型300被精确地建模。受害网203被建模为分布式电容器320a-c，其总值等于 Cgnd + 2 * K * Ccoup。 通过使用耦合的分布式负载仿真模型模拟代表性电路来精确地确定匹配传播延迟时间，来确定包括由与受害网邻近的侵扰网络的信号耦合引起的传播延迟变化的匹配传播延迟时间。 K使用K = 1 +（匹配延迟未修改延迟）/（2 * R * Ccoup）的等式确定。 R是驱动受害网的缓冲器的有效驱动电阻和相关的信号迹线电阻。
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6.发明授权Method and apparatus for determining signal line interconnect widths to ensure electromigration reliability 失效用于确定信号线互连宽度以确保电迁移可靠性的方法和装置
公开(公告)号：US6038383A
公开(公告)日：2000-03-14
申请号：US949307
申请日：1997-10-13
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5036
摘要： A method for designing and fabricating an integrated circuit is disclosed. Signal line interconnect widths are determined by performing an electromigration analysis on a trial layout of the integrated circuit. A representative circuit for an integrated circuit is designed and a trial layout is created that includes a plurality of nets. A preprocessor 505 eliminates nets that do not need further validation. An extraction process 510 generates an RC network representation of each remaining net that is to be validated to form a distributed load simulation model. Distributed capacitance and resistance of signal lines is included with load capacitance of receivers to provide an accurate profile of current flow. A profile of current flowing in the signal line of each net is determined by simulating the operation of each net using simulator 517. Peak current, RMS current and average current is determined. Post processor 520 determines if electromigration parameters are violated based on the current profile determined for each net. Widths for various segments of signal lines in the various nets are selected to be greater than or equal to a minimum width determined by post processor 520.
摘要翻译： 公开了一种用于设计和制造集成电路的方法。 通过在集成电路的试用布局上执行电迁移分析来确定信号线互连宽度。 设计用于集成电路的代表性电路，并且创建包括多个网络的试验布局。 预处理器505消除了不需要进一步验证的网络。 提取处理510生成要被验证以形成分布式负载模拟模型的每个剩余网络的RC网络表示。 信号线的分布电容和电阻包括在接收机的负载电容中，以提供电流流量的精确曲线。 通过使用模拟器517模拟每个网络的操作来确定在每个网络的信号线中流动的电流的曲线。确定峰值电流，RMS电流和平均电流。 后处理器520基于为每个网确定的当前轮廓来确定是否违反电迁移参数。 选择各网络中各信号线段的宽度大于或等于由后处理器520确定的最小宽度。
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公开(公告)号：US20100265779A1
公开(公告)日：2010-10-21
申请号：US12762297
申请日：2010-04-16
申请人： Francisco A. Cano
发明人： Francisco A. Cano
摘要： A compensatory memory system is described. This memory system substantially improves performance by adapting an associated delay in a way that optimizes circuit performance.
摘要翻译： 描述补偿性记忆系统。 该存储器系统通过以优化电路性能的方式调整相关的延迟来显着改善性能。
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公开(公告)号：US08144533B2
公开(公告)日：2012-03-27
申请号：US12762297
申请日：2010-04-16
申请人： Francisco A. Cano
发明人： Francisco A. Cano
IPC分类号： G11C7/00
摘要： A compensatory memory system is described. This memory system substantially improves performance by adapting an associated delay in a way that optimizes circuit performance.
摘要翻译： 描述补偿性记忆系统。 该存储器系统通过以优化电路性能的方式调整相关的延迟来显着改善性能。
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9.发明授权Method and apparatus for reducing failures due to bit line coupling and reducing power consumption in a memory 失效用于减少由于位线耦合引起的故障并减少存储器中的功耗的方法和装置
公开(公告)号：US5835421A
公开(公告)日：1998-11-10
申请号：US747119
申请日：1996-11-08
申请人： Luat Q. Pham , Francisco A. Cano
发明人： Luat Q. Pham , Francisco A. Cano
CPC分类号： G11C7/12
摘要： A method and apparatus for reducing failures due to bit line coupling and reducing power consumption in a memory (10). The method comprises precharging a first group of bitlines (22) to a first voltage level. Other bit lines (22) are maintained at a second voltage level. After data has been read from the memory (10), the first group of bit lines (22) is discharged to the second voltage level.
摘要翻译： 一种用于减少由于位线耦合引起的故障并降低存储器（10）中的功耗的方法和装置。 该方法包括将第一组位线（22）预充电到第一电压电平。 其他位线（22）保持在第二电压电平。 在从存储器（10）读取数据之后，第一组位线（22）被放电到第二电压电平。
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10.发明授权
公开(公告)号：US5745421A
公开(公告)日：1998-04-28
申请号：US745399
申请日：1996-11-08
申请人： Luat Q. Pham , Francisco A. Cano
发明人： Luat Q. Pham , Francisco A. Cano
摘要： A method and apparatus are disclosed for self-timing the precharge of bit lines (22) in a memory array. A reference column bit line (26) is charged to create a reference column voltage. The bit lines (22) in the memory array (12) are precharged until the reference voltage exceeds a first threshold.
摘要翻译： 公开了一种用于对存储器阵列中位线（22）的预充电进行自定时的方法和装置。 参考列位线（26）被充电以产生参考列电压。 存储器阵列（12）中的位线（22）被预充电，直到参考电压超过第一阈值。
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