公开(公告)号：US5434817A

公开(公告)日：1995-07-18

申请号：US333869

申请日：1994-11-03

申请人： Frederick A. Ware ,  John B. Dillon ,  Richard M. Barth ,  Billy W. Garrett, Jr. ,  John G. Atwood, Jr. ,  Michael P. Farmwald

发明人： Frederick A. Ware ,  John B. Dillon ,  Richard M. Barth ,  Billy W. Garrett, Jr. ,  John G. Atwood, Jr. ,  Michael P. Farmwald

IPC分类号： G06F13/16 ,  G11C5/06 ,  G11C11/401 ,  G11C7/00 ,  G06F12/06

CPC分类号： G11C5/066

摘要： As interfaces to DRAMs become more advanced and higher performance, the interfaces and signal lines required to support the interface become more expensive to implement. Therefore, it is desirable to minimize the number of signal lines and maximize the bandwidth of the signal lines interfacing to the DRAM in order to take advantage of the high performance of the signal lines in the interface. In the DRAM memory system of the present invention, the address and control lines and are combined and the information multiplexed such that the DRAM pins have roughly equal information rate at all times.

摘要翻译： 随着与DRAM的接口变得越来越先进和更高的性能，支持接口所需的接口和信号线变得越来越昂贵。 因此，为了利用接口中的信号线的高性能，期望使信号线的数量最小化并且使与DRAM接口的信号线的带宽最大化。 在本发明的DRAM存储器系统中，地址和控制线被组合并且被多路复用的信息使得DRAM引脚始终具有大致相等的信息速率。

公开(公告)号：US5430676A

公开(公告)日：1995-07-04

申请号：US202290

申请日：1994-02-25

申请人： Frederick A. Ware ,  John B. Dillon ,  Richard M. Barth ,  Billy W. Garrett, Jr. ,  John G. Atwood, Jr. ,  Michael P. Farmwald

发明人： Frederick A. Ware ,  John B. Dillon ,  Richard M. Barth ,  Billy W. Garrett, Jr. ,  John G. Atwood, Jr. ,  Michael P. Farmwald

IPC分类号： G06F13/16 ,  G11C5/06 ,  G11C11/401 ,  G06F12/00

CPC分类号： G11C5/066

摘要： As interfaces to DRAMs become more advanced and higher performance, the interfaces and signal lines required to support the interface become more expensive to implement. Therefore, it is desirable to minimize the number of signal lines and maximize the bandwidth of the signal lines interfacing to the DRAM in order to take advantage of the high performance of the signal lines in the interface. In the DRAM memory system of the present invention, the address and control lines and are combined and the information multiplexed such that the DRAM pins have roughly equal information rate at all times.

公开(公告)号：US5511024A

公开(公告)日：1996-04-23

申请号：US201981

申请日：1994-02-25

申请人： Frederick A. Ware ,  John B. Dillon ,  Richard M. Barth ,  Billy W. Garrett, Jr. ,  John G. Atwood, Jr. ,  Michael P. Farmwald

发明人： Frederick A. Ware ,  John B. Dillon ,  Richard M. Barth ,  Billy W. Garrett, Jr. ,  John G. Atwood, Jr. ,  Michael P. Farmwald

IPC分类号： G06F13/16 ,  G11C5/06 ,  G11C11/401 ,  G06F1/12

CPC分类号： G11C5/066

摘要： As interfaces to DRAMs become more advanced and higher performance, the interfaces and signal lines required to support the interface become more expensive to implement. Therefore, it is desirable to minimize the number of signal lines and maximize the bandwidth of the signal lines interfacing to the DRAM in order to take advantage of the high performance of the signal lines in the interface. In the DRAM memory system of the present invention, the address and control lines and are combined and the information multiplexed such that the DRAM pins have roughly equal information rate at all times.