公开(公告)号：US5434817A

公开(公告)日：1995-07-18

申请号：US333869

申请日：1994-11-03

申请人： Frederick A. Ware ,  John B. Dillon ,  Richard M. Barth ,  Billy W. Garrett, Jr. ,  John G. Atwood, Jr. ,  Michael P. Farmwald

发明人： Frederick A. Ware ,  John B. Dillon ,  Richard M. Barth ,  Billy W. Garrett, Jr. ,  John G. Atwood, Jr. ,  Michael P. Farmwald

IPC分类号： G06F13/16 ,  G11C5/06 ,  G11C11/401 ,  G11C7/00 ,  G06F12/06

CPC分类号： G11C5/066

摘要： As interfaces to DRAMs become more advanced and higher performance, the interfaces and signal lines required to support the interface become more expensive to implement. Therefore, it is desirable to minimize the number of signal lines and maximize the bandwidth of the signal lines interfacing to the DRAM in order to take advantage of the high performance of the signal lines in the interface. In the DRAM memory system of the present invention, the address and control lines and are combined and the information multiplexed such that the DRAM pins have roughly equal information rate at all times.

摘要翻译： 随着与DRAM的接口变得越来越先进和更高的性能，支持接口所需的接口和信号线变得越来越昂贵。 因此，为了利用接口中的信号线的高性能，期望使信号线的数量最小化并且使与DRAM接口的信号线的带宽最大化。 在本发明的DRAM存储器系统中，地址和控制线被组合并且被多路复用的信息使得DRAM引脚始终具有大致相等的信息速率。

公开(公告)号：US5430676A

公开(公告)日：1995-07-04

申请号：US202290

申请日：1994-02-25

申请人： Frederick A. Ware ,  John B. Dillon ,  Richard M. Barth ,  Billy W. Garrett, Jr. ,  John G. Atwood, Jr. ,  Michael P. Farmwald

发明人： Frederick A. Ware ,  John B. Dillon ,  Richard M. Barth ,  Billy W. Garrett, Jr. ,  John G. Atwood, Jr. ,  Michael P. Farmwald

IPC分类号： G06F13/16 ,  G11C5/06 ,  G11C11/401 ,  G06F12/00

CPC分类号： G11C5/066

摘要： As interfaces to DRAMs become more advanced and higher performance, the interfaces and signal lines required to support the interface become more expensive to implement. Therefore, it is desirable to minimize the number of signal lines and maximize the bandwidth of the signal lines interfacing to the DRAM in order to take advantage of the high performance of the signal lines in the interface. In the DRAM memory system of the present invention, the address and control lines and are combined and the information multiplexed such that the DRAM pins have roughly equal information rate at all times.

公开(公告)号：US5511024A

公开(公告)日：1996-04-23

申请号：US201981

申请日：1994-02-25

申请人： Frederick A. Ware ,  John B. Dillon ,  Richard M. Barth ,  Billy W. Garrett, Jr. ,  John G. Atwood, Jr. ,  Michael P. Farmwald

发明人： Frederick A. Ware ,  John B. Dillon ,  Richard M. Barth ,  Billy W. Garrett, Jr. ,  John G. Atwood, Jr. ,  Michael P. Farmwald

IPC分类号： G06F13/16 ,  G11C5/06 ,  G11C11/401 ,  G06F1/12

CPC分类号： G11C5/066

摘要： As interfaces to DRAMs become more advanced and higher performance, the interfaces and signal lines required to support the interface become more expensive to implement. Therefore, it is desirable to minimize the number of signal lines and maximize the bandwidth of the signal lines interfacing to the DRAM in order to take advantage of the high performance of the signal lines in the interface. In the DRAM memory system of the present invention, the address and control lines and are combined and the information multiplexed such that the DRAM pins have roughly equal information rate at all times.

公开(公告)号：US5940340A

公开(公告)日：1999-08-17

申请号：US858068

申请日：1997-05-16

申请人： Frederick A. Ware ,  John B. Dillon ,  Richard M. Barth ,  Billy Wayne Garrett, Jr. ,  John Girdner Atwood, Jr. ,  Michael P. Farmwald ,  Richard DeWitt Crisp

发明人： Frederick A. Ware ,  John B. Dillon ,  Richard M. Barth ,  Billy Wayne Garrett, Jr. ,  John Girdner Atwood, Jr. ,  Michael P. Farmwald ,  Richard DeWitt Crisp

IPC分类号： G11C7/10 ,  G11C11/401

CPC分类号： G11C7/109 ,  G11C7/1006 ,  G11C7/103 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1087

摘要： Additional operating modes are provided to enhance the functionality and performance of a memory system. In one embodiment, a unique bit mask is supplied with the write data used in each column access. In an alternate embodiment, a bit mask register and byte mask register are provided to support bit level and byte level masking. The bit mask and write data registers are realized as a single register to provide the functionality while minimizing component space and cost. In another embodiment, a separate bit mask and byte mask are provided. The byte mask is loaded with mask data in one cycle and is used during the next "q" column write accesses. This structure provides for operating modes with no bit masking, with bit masks supplied for every row access, and with bit masks supplied with every column access. In order to enhance the functionality of a system, such as a two-dimensional graphics system, in an alternate embodiment, the memory system is provided with two registers and a select control line to select data from one of two registers. In a computer graphics system, this is used to select between foreground and background colors. The embodiment can be utilized in conjunction with the other embodiments described to provide enhanced functionality and performance.

摘要翻译： 提供额外的操作模式以增强存储器系统的功能和性能。 在一个实施例中，向每个列访问中使用的写入数据提供唯一的位掩码。 在替代实施例中，提供位掩码寄存器和字节掩码寄存器以支持位电平和字节电平掩蔽。 位掩码和写数据寄存器被实现为单个寄存器，以提供功能，同时最小化组件空间和成本。 在另一个实施例中，提供单独的位掩码和字节掩码。 字节掩码在一个周期内加载掩码数据，并在下一个“q”列写入访问期间使用。 该结构提供无位掩蔽的操作模式，每行访问提供位掩码，并提供每列访问的位掩码。 为了增强诸如二维图形系统的系统的功能，在替代实施例中，存储器系统具有两个寄存器和选择控制线，以从两个寄存器之一中选择数据。 在计算机图形系统中，用于在前景和背景颜色之间进行选择。 该实施例可以与所描述的其他实施例一起使用以提供增强的功能和性能。

公开(公告)号：US5844855A

公开(公告)日：1998-12-01

申请号：US858014

申请日：1997-05-16

申请人： Frederick A. Ware ,  John B. Dillon ,  Richard M. Barth ,  Billy Wayne Garrett, Jr. ,  John Girdner Atwood, Jr. ,  Michael P. Farmwald ,  Richard DeWitt Crisp

发明人： Frederick A. Ware ,  John B. Dillon ,  Richard M. Barth ,  Billy Wayne Garrett, Jr. ,  John Girdner Atwood, Jr. ,  Michael P. Farmwald ,  Richard DeWitt Crisp

IPC分类号： G11C7/10 ,  G11C11/401

CPC分类号： G11C7/109 ,  G11C7/1006 ,  G11C7/103 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1087

摘要： Additional operating modes are provided to enhance the functionality and performance of a memory system. In one embodiment, a unique bit mask is supplied with the write data used in each column access. In an alternate embodiment, a bit mask register and byte mask register are provided to support bit level and byte level masking. The bit mask and write data registers are realized as a single register to provide the functionality while minimizing component space and cost. In another embodiment, a separate bit mask and byte mask are provided. The byte mask is loaded with mask data in one cycle and is used during the next "q" column write accesses. This structure provides for operating modes with no bit masking, with bit masks supplied for every row access, and with bit masks supplied with every column access. In order to enhance the functionality of a system, such as a two-dimensional graphics system, in an alternate embodiment, the memory system is provided with two registers and a select control line to select data from one of two registers. In a computer graphics system, this is used to select between foreground and background colors. The embodiment can be utilized in conjunction with the other embodiments described to provide enhanced functionality and performance.

公开(公告)号：US5680361A

公开(公告)日：1997-10-21

申请号：US389561

申请日：1995-02-14

申请人： Frederick A. Ware ,  John B. Dillon ,  Richard M. Barth ,  Billy Wayne Garrett, Jr. ,  John Girdner Atwood, Jr. ,  Michael P. Farmwald ,  Richard DeWitt Crisp

发明人： Frederick A. Ware ,  John B. Dillon ,  Richard M. Barth ,  Billy Wayne Garrett, Jr. ,  John Girdner Atwood, Jr. ,  Michael P. Farmwald ,  Richard DeWitt Crisp

IPC分类号： G11C7/10 ,  G11C11/401

CPC分类号： G11C7/109 ,  G11C7/1006 ,  G11C7/103 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1087

摘要： Additional modes are provided to enhance the functionality and performance of a memory system. In one embodiment, a unique bit mask is supplied with the write data used in each column access. In an alternate embodiment, a bit mask register and byte mask register are provided to support bit level and byte level masking. The bit mask and write data registers are realized as a single register to provide the functionality while minimizing component space and cost. In another embodiment, a separate bit mask and byte mask are provided. The byte mask is loaded with mask data in one cycle and is used during the next "q" column write accesses. This structure provides for operating modes with no bit masking, with bit masks supplied for every row access, and with bit masks supplied with every column access. In order to enhance the functionality of a system, such as a two-dimensional graphics system, in an alternate embodiment, the memory system is provided with two registers and a select control line to select data from one of two registers. In a computer graphics system, this is used to select between foreground and background colors. The embodiment can be utilized in conjunction with the other embodiments described to provide enhanced functionality and performance.

摘要翻译： 提供附加模式以增强存储器系统的功能和性能。 在一个实施例中，向每个列访问中使用的写入数据提供唯一的位掩码。 在替代实施例中，提供位掩码寄存器和字节掩码寄存器以支持位电平和字节电平掩蔽。 位掩码和写数据寄存器被实现为单个寄存器，以提供功能，同时最小化组件空间和成本。 在另一个实施例中，提供单独的位掩码和字节掩码。 字节掩码在一个周期内加载掩码数据，并在下一个“q”列写入访问期间使用。 该结构提供无位掩蔽的操作模式，每行访问提供位掩码，并提供每列访问的位掩码。 为了增强诸如二维图形系统的系统的功能，在替代实施例中，存储器系统具有两个寄存器和选择控制线，以从两个寄存器之一中选择数据。 在计算机图形系统中，用于在前景和背景颜色之间进行选择。 该实施例可以与所描述的其他实施例一起使用以提供增强的功能和性能。

公开(公告)号：US5956284A

公开(公告)日：1999-09-21

申请号：US167632

申请日：1998-10-06

申请人： Frederick A. Ware ,  John B. Dillon ,  Richard M. Barth ,  Billy Wayne Garrett, Jr. ,  John Girdner Atwood, Jr. ,  Michael P. Farmwald ,  Richard DeWitt Crisp

发明人： Frederick A. Ware ,  John B. Dillon ,  Richard M. Barth ,  Billy Wayne Garrett, Jr. ,  John Girdner Atwood, Jr. ,  Michael P. Farmwald ,  Richard DeWitt Crisp

IPC分类号： G11C7/10 ,  G11C11/401

CPC分类号： G11C7/109 ,  G11C7/1006 ,  G11C7/103 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1087

摘要： Additional operating modes are provided to enhance the functionality and performance of a memory system. In one embodiment, a unique bit mask is supplied with the write data used in each column access. In an alternate embodiment, a bit mask register and byte mask register are provided to support bit level and byte level masking. The bit mask and write data registers are realized as a single register to provide the functionality while minimizing component space and cost. In another embodiment, a separate bit mask and byte mask are provided. The byte mask is loaded with mask data in one cycle and is used during the next "q" column write accesses. This structure provides for operating modes with no bit masking, with bit masks supplied for every row access, and with bit masks supplied with every column access. In order to enhance the functionality of a system, such as a two-dimensional graphics system, in an alternate embodiment, the memory system is provided with two registers and a select control line to select data from one of two registers. In a computer graphics system, this is used to select between foreground and background colors. The embodiment can be utilized in conjunction with the other embodiments described to provide enhanced functionality and performance.

公开(公告)号：US5446696A

公开(公告)日：1995-08-29

申请号：US347770

申请日：1994-12-02

申请人： Frederick A. Ware ,  James A. Gasbarro ,  John B. Dillon ,  Michael P. Farmwald ,  Mark A. Horowitz ,  Matthew M. Griffin

发明人： Frederick A. Ware ,  James A. Gasbarro ,  John B. Dillon ,  Michael P. Farmwald ,  Mark A. Horowitz ,  Matthew M. Griffin

IPC分类号： G11C11/407 ,  G11C11/401 ,  G11C11/406 ,  G11G7/00

CPC分类号： G11C11/406

摘要： A synchronous DRAM system with internal refresh is controlled by a refresh signal issued by an oscillator or memory controller coupled to the DRAM. By locating the oscillator on the processor or memory controller better control of the frequency of refresh is achieved, particularly, as the signal can be derived from a crystal which is not sensitive to variations in operating conditions. The oscillator drives a refresh signal on a bus or signal line to the DRAM, such that the refresh address counter is incremented and the row identified by the refresh address counter is refreshed.

摘要翻译： 具有内部刷新的同步DRAM系统由耦合到DRAM的振荡器或存储器控制器发出的刷新信号控制。 通过将振荡器定位在处理器或存储器控制器上，可以更好地控制刷新频率，特别是可以从对操作条件变化不敏感的晶体导出信号。 振荡器将总线或信号线上的刷新信号驱动到DRAM，使得刷新地址计数器递增，刷新地址计数器识别的行被刷新。

公开(公告)号：US5337285A

公开(公告)日：1994-08-09

申请号：US65804

申请日：1993-05-21

申请人： Frederick A. Ware ,  James A. Gasbarro ,  John B. Dillon ,  Matthew M. Griffin ,  Richard M. Barth ,  Mark A. Horowitz

发明人： Frederick A. Ware ,  James A. Gasbarro ,  John B. Dillon ,  Matthew M. Griffin ,  Richard M. Barth ,  Mark A. Horowitz

IPC分类号： G06F1/32 ,  G11C5/14 ,  H03K19/00 ,  H03K19/0175 ,  G11C7/00

CPC分类号： G11C5/14

摘要： A power control circuit to minimize power consumption of CMOS circuits by disabling/enabling the clock input to the CMOS circuit. A phase locked loop (PLL) or delay locked loop (DLL) drives a capacitive load of the component and a dummy load comparable to the component load. A standby latch is provided to control the clock input to the component. In a standby state, the clock signal is not provided to the component but the PLL/DLL continues to operate, driving the dummy load. Thus, when it is desirable to power on the circuit, the standby latch is reset and the clock signal is provided to the component, thereby turning on the component with little latency.

摘要翻译： 电源控制电路，通过禁止/使能CMOS电路的时钟输入来最小化CMOS电路的功耗。 锁相环（PLL）或延迟锁定环（DLL）驱动组件的容性负载和与组件负载相当的虚拟负载。 提供备用锁存器来控制对组件的时钟输入。 在待机状态下，时钟信号不提供给组件，但PLL / DLL继续运行，驱动虚拟负载。 因此，当期望对电路通电时，备用锁存器被复位，并且时钟信号被提供给部件，从而以很小的延迟打开部件。

公开(公告)号：US06356975B1

公开(公告)日：2002-03-12

申请号：US09169526

申请日：1998-10-09

申请人： Richard M. Barth ,  Ely K. Tsern ,  Mark A. Horowitz ,  Donald C. Stark ,  Craig E. Hampel ,  Frederick A. Ware ,  John B. Dillon ,  by Nancy David Dillon

发明人： Richard M. Barth ,  Ely K. Tsern ,  Mark A. Horowitz ,  Donald C. Stark ,  Craig E. Hampel ,  Frederick A. Ware ,  John B. Dillon ,  by Nancy David Dillon

IPC分类号： G06F1200

CPC分类号： G11C7/1006 ,  G06F13/1615 ,  G11C7/10 ,  G11C7/1039 ,  G11C8/12 ,  G11C11/4076

摘要： A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and write, which handle the primitive operations of the memory core to which the operation units are coupled. The memory device further includes a plurality of transport units configured to obtain information from external connections specifying an operation for one of the operation units and to transfer data between the memory core and the external connections. The transport units operate concurrently with the operation units as added stages to the pipeline, thereby creating a memory device which operates at high throughput and with low service times under the memory reference stream of common applications.