公开(公告)号：US20170047933A1

公开(公告)日：2017-02-16

申请号：US14994197

申请日：2016-01-13

Applicant: Freescale Semiconductor, Inc.

Inventor： Pierre SAVARY ,  Birama GOUMBALLA ,  Didier SALLE

IPC: H03L7/099 ,  H03L7/085 ,  H03L7/08

CPC classification number: H03L7/085

Abstract: A phase locked loop circuit includes a voltage controlled oscillator, VCO, configured to receive an oscillator tuning voltage; a phase detector configured to receive an input signal and a reference signal and generate a phase difference pulse signal that is varied in accordance with the oscillator tuning voltage; a loop filter having an input and an output; and a level shifter circuit coupled to an output of the phase detector and the loop filter input and configured to apply a level shift to the phase difference pulse signal such that the level shift is configured to compensate VCO gain and the loop filter averages the phase difference pulse signal to output an averaged signal to the VCO.

Abstract translation: 锁相环电路包括被配置为接收振荡器调谐电压的压控振荡器VCO; 相位检测器，被配置为接收输入信号和参考信号，并产生根据振荡器调谐电压而变化的相位差脉冲信号; 具有输入和输出的环路滤波器; 以及电平移位器电路，耦合到相位检测器和环路滤波器输入的输出端，并被配置为向相位差脉冲信号施加电平移位，使得电平移位被配置为补偿VCO增益，并且环路滤波器平均相位差 脉冲信号以将平均信号输出到VCO。

公开(公告)号：US20170040943A1

公开(公告)日：2017-02-09

申请号：US14991043

申请日：2016-01-08

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Cristian PAVAO-MOREIRA ,  Olivier Vincent DOARE ,  Birama GOUMBALLA ,  Didier SALLE

IPC: H03B5/12

CPC classification number: H03B5/1265 ,  H01G15/00 ,  H03B5/1212 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1293 ,  H03L7/099

Abstract: An electronic device comprises a controllable capacitor bank and a capacitive divider arranged in parallel with the capacitor bank and configured to linearize the capacitor bank in a linearization frequency range of a frequency characteristic of the electronic device. The capacitive divider comprises a series arrangement of a first series capacitance, and a main capacitor bank. A control circuit coupled to one or more control inputs of the capacitive divider and controllable capacitor bank is configured to modify the equivalent capacitance of the capacitive divider and the controllable capacitor bank for providing capacitance steps, each capacitance step being variable over frequency such that for each step a frequency change Δf of the frequency characteristic is maintained constant in the linearization frequency range.

Abstract translation: 电子设备包括可控电容器组和与电容器组并联布置的电容分压器，并且被配置为在电子器件的频率特性的线性化频率范围内使电容器组线性化。 电容分压器包括第一串联电容和主电容器组的串联布置。 耦合到电容分压器和可控电容器组的一个或多个控制输入的控制电路被配置为修改电容分压器和可控电容器组的等效电容以提供电容步长，每个电容步长可在频率上变化，使得对于每个 频率特性的频率变化Δf在线性化频率范围内保持恒定。