公开(公告)号：US09904313B2

公开(公告)日：2018-02-27

申请号：US14797285

申请日：2015-07-13

Applicant: Freescale Semiconductor, Inc.

Inventor： Ron-Michael Bar ,  Eran Glickman ,  Sagi Gurfinkel

IPC: G06F1/00 ,  G06F1/12 ,  G06F1/14

CPC classification number: G06F1/12 ,  G06F1/14

Abstract: In a processing system, a method includes selecting, at a timer management component of a processor, a timer ring of a set of timer rings for a requested timer based on a time unit granularity associated with the requested timer, wherein each timer ring of the set has a different time unit granularity. The method further includes instantiating the requested timer in a selected entry of the selected timer ring. Instantiating the requested timer may include fixedly maintaining a record for the requested timer in the selected entry of the selected timer ring for the entire time span of the requested timer.

公开(公告)号：US09921637B2

公开(公告)日：2018-03-20

申请号：US14922348

申请日：2015-10-26

Applicant: Freescale Semiconductor, Inc.

Inventor： Dmitriy Shurin ,  Ron-Michael Bar ,  Eran Glickman

IPC: G06F1/32

CPC classification number: G06F1/3268 ,  G06F1/3206 ,  G06F1/3287 ,  Y02D10/154 ,  Y02D10/171

Abstract: Multi-port power prediction for power management of data storage devices is disclosed. For certain embodiments, a host interface within a port multiplier receives host messages from a host device for a plurality of data storage devices. The port multiplier then uses a plurality of ports to forward device messages to the data storage devices based upon the host messages. A power prediction controller determines target data storage devices for access commands within the host messages and generates power commands to adjust power modes for target data storage devices to place the target data storage devices in active power modes prior to access according to the access commands from the host device. Power up latency is thereby reduced or eliminated for the target data storage devices.

公开(公告)号：US20170115723A1

公开(公告)日：2017-04-27

申请号：US14922348

申请日：2015-10-26

Applicant: Freescale Semiconductor, Inc.

Inventor： Dmitriy Shurin ,  Ron-Michael Bar ,  Eran Glickman

IPC: G06F1/32

CPC classification number: G06F1/3268 ,  G06F1/3206 ,  G06F1/3287 ,  Y02D10/154 ,  Y02D10/171

Abstract: Multi-port power prediction for power management of data storage devices is disclosed. For certain embodiments, a host interface within a port multiplier receives host messages from a host device for a plurality of data storage devices. The port multiplier then uses a plurality of ports to forward device messages to the data storage devices based upon the host messages. A power prediction controller determines target data storage devices for access commands within the host messages and generates power commands to adjust power modes for target data storage devices to place the target data storage devices in active power modes prior to access according to the access commands from the host device. Power up latency is thereby reduced or eliminated for the target data storage devices.

公开(公告)号：US20170017259A1

公开(公告)日：2017-01-19

申请号：US14797286

申请日：2015-07-13

Applicant: Freescale Semiconductor, Inc.

Inventor： Ron-Michael Bar ,  Evgeni Ginzburg ,  Eran Glickman

IPC: G06F1/10

CPC classification number: G06F1/10 ,  G06F9/4825

Abstract: In a processing system, a method includes transmitting a timer expiration notification from a timer management component of a processor to one or more other components of the processor in response to expiration of a timer. The method further includes transmitting, from a component of the processor that requested instantiation of the timer, a timer release confirmation message to the timer management component in response to the timer expiration notification, the timer release confirmation message confirming that the component has released the timer. The method also includes preventing reallocation of a timer identifier (ID) associated with the timer to another timer after the expiration of the timer and until receipt of the timer release confirmation message at the timer management component.

Abstract translation: 在处理系统中，一种方法包括响应于定时器的到期，将定时器到期通知从处理器的定时器管理组件发送到处理器的一个或多个其它组件。 该方法还包括：响应于定时器到期通知，从定时器释放确认消息向定时器管理组件发送请求实例化定时器的处理器的组件，定时器释放确认消息确认组件已经释放定时器 。 该方法还包括在定时器到期之后防止与定时器相关联的定时器标识符（ID）重定位到另一个定时器，并且直到定时器管理组件接收到定时器释放确认消息。

公开(公告)号：US09813242B2

公开(公告)日：2017-11-07

申请号：US14749749

申请日：2015-06-25

Applicant: Freescale Semiconductor, Inc.

Inventor： Ron-Michael Bar ,  Yaron Alankry ,  Eran Glickman

IPC: G06F21/50 ,  G06F21/55 ,  G06F21/87 ,  H04L9/30 ,  G06F12/14

CPC classification number: H04L9/30 ,  G06F12/14 ,  G06F21/50 ,  G06F21/55 ,  G06F21/87 ,  G06F2212/72 ,  H04L9/3297

Abstract: An integrated circuit (IC) package includes a storage element and a protection component coupled to the storage element. The protection component includes a breach detection component configured to detect an attempted breach of the IC package. The protection component further includes a time detection component configured to determine a breach timestamp associated with a time of occurrence of the attempted breach and configured to store a representation of the breach timestamp in the storage element. The storage element may be configured to store a sensitive datum, and the time detection component may be configured to store the representation of the breach timestamp by overwriting the sensitive datum in the storage element with the representation of the breach timestamp.

公开(公告)号：US20170017260A1

公开(公告)日：2017-01-19

申请号：US14797285

申请日：2015-07-13

Applicant: Freescale Semiconductor, Inc.

Inventor： Ron-Michael Bar ,  Eran Glickman ,  Sagi Gurfinkel

IPC: G06F1/12

CPC classification number: G06F1/12 ,  G06F1/14

Abstract: In a processing system, a method includes selecting, at a timer management component of a processor, a timer ring of a set of timer rings for a requested timer based on a time unit granularity associated with the requested timer, wherein each timer ring of the set has a different time unit granularity. The method further includes instantiating the requested timer in a selected entry of the selected timer ring. Instantiating the requested timer may include fixedly maintaining a record for the requested timer in the selected entry of the selected timer ring for the entire time span of the requested timer.

Abstract translation: 在处理系统中，一种方法包括：在处理器的定时器管理组件处，基于与所请求的定时器相关联的时间单位粒度，选择所请求的定时器的一组定时器环的定时器环，其中每个定时器环 集合具有不同的时间单位粒度。 该方法还包括在选定的定时器环的选定条目中实例化所请求的定时器。 所请求的定时器的实例化可以包括在所请求的定时器的整个时间间隔内，在选定的定时器环的所选择的条目中固定地维护所请求的定时器的记录。

公开(公告)号：US20160380769A1

公开(公告)日：2016-12-29

申请号：US14749749

申请日：2015-06-25

Applicant: Freescale Semiconductor, Inc.

Inventor： Ron-Michael Bar ,  Yaron Alankry ,  Eran Glickman

IPC: H04L9/30 ,  G06F12/14

CPC classification number: H04L9/30 ,  G06F12/14 ,  G06F21/50 ,  G06F21/55 ,  G06F21/87 ,  G06F2212/72 ,  H04L9/3297

Abstract: An integrated circuit (IC) package includes a storage element and a protection component coupled to the storage element. The protection component includes a breach detection component configured to detect an attempted breach of the IC package. The protection component further includes a time detection component configured to determine a breach timestamp associated with a time of occurrence of the attempted breach and configured to store a representation of the breach timestamp in the storage element. The storage element may be configured to store a sensitive datum, and the time detection component may be configured to store the representation of the breach timestamp by overwriting the sensitive datum in the storage element with the representation of the breach timestamp.

Abstract translation: 集成电路（IC）封装包括存储元件和耦合到存储元件的保护元件。 保护部件包括配置成检测尝试违反IC封装的漏损检测部件。 保护组件还包括时间检测组件，其被配置为确定与尝试违规的发生时间相关联的违例时间戳，并且被配置为将存储元件中的违例时间戳的表示存储。 存储元件可以被配置为存储敏感数据，并且时间检测组件可以被配置为通过用破坏时间戳的表示覆盖存储元件中的敏感数据来存储违约时间戳的表示。

公开(公告)号：US09915969B2

公开(公告)日：2018-03-13

申请号：US14797286

申请日：2015-07-13

Applicant: Freescale Semiconductor, Inc.

Inventor： Ron-Michael Bar ,  Evgeni Ginzburg ,  Eran Glickman

IPC: G06F1/04 ,  G06F1/10

CPC classification number: G06F1/10 ,  G06F9/4825

Abstract: In a processing system, a method includes transmitting a timer expiration notification from a timer management component of a processor to one or more other components of the processor in response to expiration of a timer. The method further includes transmitting, from a component of the processor that requested instantiation of the timer, a timer release confirmation message to the timer management component in response to the timer expiration notification, the timer release confirmation message confirming that the component has released the timer. The method also includes preventing reallocation of a timer identifier (ID) associated with the timer to another timer after the expiration of the timer and until receipt of the timer release confirmation message at the timer management component.