公开(公告)号：US20220083836A1

公开(公告)日：2022-03-17

申请号：US17532999

申请日：2021-11-22

申请人： Fu-Chang Hsu ,  Kevin Hsu

发明人： Fu-Chang Hsu ,  Kevin Hsu

IPC分类号： G06N3/04

摘要： Configurable three-dimensional neural network array. In an exemplary embodiment, a three-dimensional (3D) neural network array includes a plurality of stacked synapse layers having a first orientation, and a plurality of synapse lines having a second orientation and passing through the synapse layers. The neural network array also includes synapse elements connected between the synapse layers and synapse lines. Each synapse element includes a programmable resistive element. The neural network array also includes a plurality of output neurons, and a plurality of select transistors connected between the synapse lines and the output neurons. The gate terminals of the select transistors receive input signals.

公开(公告)号：US11723288B2

公开(公告)日：2023-08-08

申请号：US17209107

申请日：2021-03-22

申请人： Fu-Chang Hsu ,  Kevin Hsu

发明人： Fu-Chang Hsu ,  Kevin Hsu

IPC分类号： G06N10/00 ,  H10N60/10 ,  H03K3/38 ,  H10N69/00

CPC分类号： H10N60/11 ,  G06N10/00 ,  H03K3/38 ,  H10N60/128 ,  H10N69/00

摘要： A quantum bit array is disclosed. In an embodiment, the quantum bit array includes a control gate coupled to a qubit and at least one pass gate coupled between the qubit and an adjacent qubit to control operation of the qubit of the quantum bit array, a bit line, and a first transistor channel that connects the bit line to the control gate. The array further comprises at least one word line coupled to the first transistor channel. The at least one word line selectively controls charge flow through the first transistor channel. The array further comprises a capacitor coupled to selectively store charge in the first transistor channel.

公开(公告)号：US12029140B2

公开(公告)日：2024-07-02

申请号：US18365936

申请日：2023-08-04

申请人： Fu-Chang Hsu ,  Kevin Hsu

发明人： Fu-Chang Hsu ,  Kevin Hsu

IPC分类号： H10N60/10 ,  G06N10/00 ,  H03K3/38 ,  H10N69/00

CPC分类号： H10N60/11 ,  G06N10/00 ,  H03K3/38 ,  H10N60/128 ,  H10N69/00

摘要： A quantum bit array is disclosed. In an embodiment, the quantum bit array includes a control gate coupled to a qubit and at least one pass gate coupled between the qubit and an adjacent qubit to control operation of the qubit of the quantum bit array, a bit line, and a first transistor channel that connects the bit line to the control gate. The array further comprises at least one word line coupled to the first transistor channel. The at least one word line selectively controls charge flow through the first transistor channel. The array further comprises a capacitor coupled to selectively store charge in the first transistor channel.

公开(公告)号：US11205116B2

公开(公告)日：2021-12-21

申请号：US15835375

申请日：2017-12-07

申请人： Fu-Chang Hsu ,  Kevin Hsu

发明人： Fu-Chang Hsu ,  Kevin Hsu

IPC分类号： G06N3/063 ,  G06N3/04

摘要： Three-dimensional neural network array. In an exemplary embodiment, a three-dimensional (3D) neural network includes a plurality of input conductors forming a plurality of stacked input layers having a first orientation, and at least one output conductor forming an output layer having the first orientation. The three-dimensional (3D) neural network also includes a plurality of hidden conductors having a second orientation. Each hidden conductor includes an in-line threshold element. The three-dimensional (3D) neural network also includes synapse elements coupled between the hidden conductors and the input conductors and between the hidden conductors and the output conductor. Each synapse element includes a programmable resistive element.

公开(公告)号：US11182664B2

公开(公告)日：2021-11-23

申请号：US16006727

申请日：2018-06-12

申请人： Fu-Chang Hsu ,  Kevin Hsu

发明人： Fu-Chang Hsu ,  Kevin Hsu

IPC分类号： G06N3/04

摘要： Configurable three-dimensional neural network array. In an exemplary embodiment, a three-dimensional (3D) neural network array includes a plurality of stacked synapse layers having a first orientation, and a plurality of synapse lines having a second orientation and passing through the synapse layers. The neural network array also includes synapse elements connected between the synapse layers and synapse lines. Each synapse element includes a programmable resistive element. The neural network array also includes a plurality of output neurons, and a plurality of select transistors connected between the synapse lines and the output neurons. The gate terminals of the select transistors receive input signals.

公开(公告)号：US20180157964A1

公开(公告)日：2018-06-07

申请号：US15821679

申请日：2017-11-22

申请人： Fu-Chang Hsu ,  Kevin Hsu

发明人： Fu-Chang Hsu ,  Kevin Hsu

IPC分类号： G06N3/04 ,  G06N3/063

CPC分类号： G06N3/04 ,  G06N3/063

摘要： A high-density neural network array. In an exemplary embodiment, an apparatus includes a three-dimensional (3D) structure having a plurality of layers forming a neural network. Each layer comprises one or more conductors forming neurons with each neuron having neuron inputs and neuron outputs. The apparatus also includes synapse elements coupled between the neurons outputs and the neuron inputs of neurons in adjacent layers. Each synapse element comprises a material that applies a selected weight to signals passing between neurons connected to that synapse element.

公开(公告)号：US20210296556A1

公开(公告)日：2021-09-23

申请号：US17209107

申请日：2021-03-22

申请人： Fu-Chang Hsu ,  Kevin Hsu

发明人： Fu-Chang Hsu ,  Kevin Hsu

IPC分类号： H01L39/22 ,  H01L27/18 ,  H03K3/38 ,  G06N10/00

摘要： A quantum bit array is disclosed. In an embodiment, the quantum bit array includes a control gate coupled to a qubit and at least one pass gate coupled between the qubit and an adjacent qubit to control operation of the qubit of the quantum bit array, a bit line, and a first transistor channel that connects the bit line to the control gate. The array further comprises at least one word line coupled to the first transistor channel. The at least one word line selectively controls charge flow through the first transistor channel. The array further comprises a capacitor coupled to selectively store charge in the first transistor channel.

公开(公告)号：US20190108437A1

公开(公告)日：2019-04-11

申请号：US16006730

申请日：2018-06-12

申请人： Fu-Chang Hsu ,  Kevin Hsu

发明人： Fu-Chang Hsu ,  Kevin Hsu

IPC分类号： G06N3/063 ,  G06N3/04

摘要： Two and three-dimensional neural network arrays. In an exemplary embodiment, a two-dimensional (2D) neural network array includes a plurality of input neurons connected to a plurality of input lines, and a plurality of output neurons connected to a plurality of output lines. The 2D neural network array also includes synapse elements connected between the input lines and the output lines. Each synapse element includes a programmable resistive element. A three-dimensional (3D) neural network array includes a plurality of stacked two-dimensional (2D) neural network arrays each having a plurality of input neurons connected to a plurality of input layers and a plurality of output neurons connected to a plurality of output layers. The output layers intersect with the input layers and include synapse elements formed between intersecting regions of the input layers and the output layers. Each synapse element includes a programmable resistive element.

公开(公告)号：US20180165573A1

公开(公告)日：2018-06-14

申请号：US15835375

申请日：2017-12-07

申请人： Fu-Chang Hsu ,  Kevin Hsu

发明人： Fu-Chang Hsu ,  Kevin Hsu

IPC分类号： G06N3/063 ,  G06N3/04

CPC分类号： G06N3/063 ,  G06N3/04 ,  G06N3/0454

摘要： Three-dimensional neural network array. In an exemplary embodiment, a three-dimensional (3D) neural network includes a plurality of input conductors forming a plurality of stacked input layers having a first orientation, and at least one output conductor forming an output layer having the first orientation. The three-dimensional (3D) neural network also includes a plurality of hidden conductors having a second orientation. Each hidden conductor includes an in-line threshold element. The three-dimensional (3D) neural network also includes synapse elements coupled between the hidden conductors and the input conductors and between the hidden conductors and the output conductor. Each synapse element includes a programmable resistive element.

公开(公告)号：US20220164638A1

公开(公告)日：2022-05-26

申请号：US17535510

申请日：2021-11-24

申请人： Fu-Chang Hsu ,  Kevin Hsu

发明人： Fu-Chang Hsu ,  Kevin Hsu

IPC分类号： G06N3/063 ,  G06N3/04

摘要： Methods and apparatus for neural network arrays are disclosed. In an embodiment, a neural network array includes a plurality of strings, each string having a drain select gate transistor connected to a plurality of non-volatile memory cells that are connected in series and function as synapses, and a plurality of output nodes, each output node connected to receive output signals from a plurality of drain terminals of the drain select gates. The array also includes a plurality of input nodes, each input node connected to provide input signals to a plurality of gate terminals of the drain select gates, and a plurality of weight select signals connected to the plurality of non-volatile memory cells in each string, respectively. Each weight select signal provides a selected voltage to a selected non-volatile memory cell to cause the selected non-volatile memory cell to conduct current according to a selected characteristic of the selected non-volatile memory cell.