公开(公告)号：US20030133337A1

公开(公告)日：2003-07-17

申请号：US10300592

申请日：2002-11-21

Applicant: FUJITSU LIMITED

Inventor： Yoshikazu Yamada ,  Koichi Kuroiwa ,  Shoji Taniguchi ,  Takanobu Kashiwagi

IPC: G11C007/00

CPC classification number: H04B1/40 ,  H04W52/028 ,  Y02D70/24 ,  Y02D70/40

Abstract: A proposed semiconductor device is directed to making unnecessary circuit operation inactive to reduce power consumption because of leakage current. The device is functionally divided into blocks. The power supply systems of the blocks are divided into a non-controlled power supply group in which power is always on and controlled power supply groups in each of which groups a supply of power can be turned on/off independently. When a power supply system control part of the non-controlled power supply group outputs a control signal for power on, a power switch part turns on to release the controlled power supply group from the sleep mode, so that the first processing part starts intermittent operation. Only when it is determined that a first next-processing necessity determining part determines necessity of the next processing, a control signal is generated to activate the next power supply group. The blocks unnecessary for processing are not supplied with power, so that no leakage current flows and power consumption because thereof can be reduced.

Abstract translation: 所提出的半导体器件旨在使不必要的电路操作无效以便由于泄漏电流而降低功耗。 该设备在功能上划分为块。 块的电源系统分为电源始终接通的非受控电源组，每个组中的电源组可独立接通/断开。 当非受控电源组的电源系统控制部分输出用于接通电源的控制信号时，电源开关部分接通以将受控电源组从睡眠模式释放，使得第一处理部分开始间歇操作 。 只有当确定第一下一个处理必要性确定部分确定下一个处理的必要性时，才产生控制信号以激活下一个电源组。 不需要处理的块被供电，所以不会有泄漏电流流动，因此可以减少功耗。

公开(公告)号：US20030146462A1

公开(公告)日：2003-08-07

申请号：US10346103

申请日：2003-01-17

Applicant: FUJITSU LIMITED

Inventor： Jun Iwata ,  Shoji Taniguchi ,  Koichi Kuroiwa ,  Yoshikazu Yamada

IPC: H01L027/108 ,  H01L029/04 ,  H01L029/76

CPC classification number: G06F1/3203 ,  G06F1/3287 ,  H04W52/028 ,  Y02D10/171 ,  Y02D70/24

Abstract: A semiconductor device that quickly saves data stored in an area to which power is supplied intermittently. Power is supplied intermittently to a first area. Power is supplied continuously to a second area. A memory is located in the second area. A save circuit saves data used in the first area in the memory before the supply of power being stopped. A restoration circuit restores data which has been saved in the memory to a predetermined circuit in the first area. A power supply control circuit supplies power to the memory if data has been saved in the memory. Otherwise the power supply control circuit stops the supply of power to the memory.

Abstract translation: 一种半导体器件，其能够快速地保存间歇地供电的区域中存储的数据。 间歇地供电到第一区域。 电源连续供应到第二个区域。 内存位于第二区。 节电电路在电源供电停止之前，将存储器中第一个区域中使用的数据保存在存储器中。 恢复电路将保存在存储器中的数据恢复到第一区域中的预定电路。 如果数据已被保存在存储器中，则电源控制电路向存储器供电。 否则电源控制电路停止向存储器供电。

公开(公告)号：US20030042972A1

公开(公告)日：2003-03-06

申请号：US10097619

申请日：2002-03-15

Applicant: FUJITSU LIMITED

Inventor： Yoshikazu Yamada ,  Masami Kanasugi ,  Shoji Taniguchi ,  Koichi Kuroiwa

IPC: G05F001/10

CPC classification number: G06F1/3237 ,  G06F1/3203 ,  Y02D10/128

Abstract: A semiconductor integrated circuit includes a plurality of functional blocks, each of which starts and stops an operation thereof in response to assertion and negation, respectively, of a corresponding command signal, a clock generation circuit which generates a clock signal, a clock control circuit which starts supplying the clock signal to each of the functional blocks in response to the assertion of the corresponding command signal, and stops supplying the clock signal to each of the functional blocks in response to the negation of the corresponding command signal.

公开(公告)号：US20030026328A1

公开(公告)日：2003-02-06

申请号：US10102814

申请日：2002-03-22

Applicant: Fujitsu Limited

Inventor： Yoshikazu Yamada ,  Shoji Taniguchi ,  Koichi Kuroiwa ,  Masami Kanasugi

IPC: H04K001/00

CPC classification number: H04B1/7113 ,  H04B2201/7071

Abstract: A receiving unit, receiving method, and semiconductor device that reduce the size of circuits in a receiving unit. A receiving section receives signals sent from a base station and transmitted through a plurality of paths. A path tracking section detects timing of each of the plurality of paths through which the signals received by the receiving section were transmitted. A demodulating section demodulates the received signals by performing a despreading process according to the timing of the plurality of paths detected by the path tracking section. A correlation value calculating section calculates a correlation value between the received signals and a spreading code. A destination selecting section provides output from the correlation value calculating section to the path tracking section in the case of performing a path tracking process by the path tracking section and provides output from the correlation value calculating section to the demodulating section in the case of demodulating the received signals by the demodulating section.

Abstract translation: 一种减小接收单元中的电路尺寸的接收单元，接收方法和半导体器件。 接收部分接收从基站发送并通过多个路径发送的信号。 路径跟踪部分检测发送由接收部分接收的信号的多个路径中的每一个的定时。 解调部通过根据由路径追踪部检测出的多个路径的定时进行解扩处理来解调接收信号。 相关值计算部分计算接收信号和扩展码之间的相关值。 目的地选择部分在路径跟踪部分执行路径跟踪处理的情况下，将相关值计算部分的输出提供给路径跟踪部分，并且在解调该解调部分的情况下将相关值计算部分的输出提供给解调部分 由解调部分接收信号。

公开(公告)号：US20030067965A1

公开(公告)日：2003-04-10

申请号：US10105191

申请日：2002-03-26

Applicant: FUJITSU LIMITED of KAWASAKI, JAPAN

Inventor： Shoji Taniguchi ,  Koichi Kuroiwa ,  Masami Kanasugi ,  Yoshikazu Yamada ,  Mahiro Hikita

IPC: H04K001/00

CPC classification number: H04B1/7115 ,  H04B1/712

Abstract: A receiving unit for receiving a CDMA system signal having a plurality of multipath components is intended to reduce the size. A receiving section receives a CDMA system signal. A storage section stores the signal received by the receiving section. A demodulation section demodulates each of multipath components included in the received signal stored in the storage section with a despreading code. A control section controls for demodulating a plurality of the multipath components by causing the demodulation section to perform a time division multiplex process. A Rake combining section performs the maximal ratio combining of output from the demodulation section to generate a demodulated signal.

Abstract translation: 用于接收具有多个多径分量的CDMA系统信号的接收单元旨在减小尺寸。 接收部分接收CDMA系统信号。 存储部存储由接收部接收的信号。 解调部分用解扩码解调包含在存储部分中的接收信号中的每个多径分量。 控制部分通过使解调部分进行时分复用处理来控制多个多径分量的解调。 Rake组合部分执行来自解调部分的输出的最大比组合以产生解调信号。

公开(公告)号：US20030009499A1

公开(公告)日：2003-01-09

申请号：US10078368

申请日：2002-02-21

Applicant: FUJITSU LIMITED

Inventor： Koichi Kuroiwa ,  Shoji Taniguchi ,  Masami Kanasugi ,  Yoshikazu Yamada

IPC: G06F007/38

CPC classification number: G06F9/3001

Abstract: There are provided an arithmetic unit and a receiver unit which execute an arithmetic operation at a high speed and allow reduction of the size thereof. An input section inputs data of the data group. First to n-th (n>1) storage sections have a capacity capable of storing at least part or all of the data group. A readout section selects one of the first to n-th storage sections and reads out therefrom a data group already stored therein. An arithmetic section performs a predetermined arithmetic operation between the data group read out by the readout section and the data group newly inputted by the input section. A writing section writes a result of the predetermined arithmetic operation by the arithmetic section in a predetermined one of the storage sections, which is not selected by the reading section as the one from which the data group already stored therein is to be read out.

Abstract translation: 提供了一种算术单元和接收器单元，其高速执行算术运算并允许其尺寸的减小。 输入部分输入数据组的数据。 第一至第n（n> 1）个存储部具有能够存储至少部分或全部数据组的容量。 读出部选择第一至第n存储部中的一个，并从其中读出已经存储在其中的数据组。 算术部分在由读出部分读出的数据组与由输入部分新输入的数据组之间进行预定的算术运算。 写入部分将未被读取部分选择的预定的一个存储部分中的运算部分的预定算术运算的结果写入其中已经存储在其中的数据组被读出。