公开(公告)号：US11101224B2

公开(公告)日：2021-08-24

申请号：US15877283

申请日：2018-01-22

Applicant: Futurewei Technologies, Inc.

Inventor： Shiqun Gu ,  Tiejun Liu ,  Zhao Chen

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/522 ,  H01L21/768 ,  H01L23/498

Abstract: Techniques and structures for improving shielding of an integrated circuit package are provided. The integrated circuit package includes a die including a plurality of bump sites and a substrate connected to the die at the plurality of bump sites. The substrate includes at least one layer that implements one or more signal traces and a plurality of shield traces. Each shield trace in the plurality of shield traces is coupled to a ground plane by a plurality of slot vias.

公开(公告)号：US20180358303A1

公开(公告)日：2018-12-13

申请号：US15877283

申请日：2018-01-22

Applicant: Futurewei Technologies, Inc.

Inventor： Shiqun Gu ,  Tiejun Liu ,  Zhao Chen

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/522 ,  H01L23/498 ,  H01L21/768

CPC classification number: H01L23/552 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/49827 ,  H01L23/5226 ,  H01L24/14 ,  H01L24/17 ,  H01L2924/14 ,  H01L2924/15321 ,  H01L2924/3025

Abstract: Techniques and structures for improving shielding of an integrated circuit package are provided. The integrated circuit package includes a die including a plurality of bump sites and a substrate connected to the die at the plurality of bump sites. The substrate includes at least one layer that implements one or more signal traces and a plurality of shield traces. Each shield trace in the plurality of shield traces is coupled to a ground plane by a plurality of slot vias.