公开(公告)号：US20140361375A1

公开(公告)日：2014-12-11

申请号：US13910370

申请日：2013-06-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Derya DENIZ

IPC: H01L21/283 ,  H01L29/45

CPC classification number: H01L29/517 ,  H01L21/283 ,  H01L21/28512 ,  H01L21/28518 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/45 ,  H01L29/456 ,  H01L29/78

Abstract: A semiconductor device with an n-type transistor and a p-type transistor having an active region is provided. The active region further includes two adjacent gate structures. A portion of a dielectric layer between the two adjacent gate structures is selectively removed to form a contact opening having a bottom and sidewalls over the active region. A bilayer liner is selectively provided within the contact opening in the n-type transistor and a monolayer liner is provided within the contact opening in the p-type transistor. The contact opening in the n-type transistor and p-type transistor is filled with contact material. The monolayer liner is treated to form a silicide lacking nickel in the p-type transistor.

Abstract translation: 提供具有n型晶体管和具有有源区的p型晶体管的半导体器件。 有源区还包括两个相邻的门结构。 选择性地去除两个相邻栅极结构之间的介电层的一部分，以形成具有底部和活性区上侧壁的接触开口。 双层衬垫选择性地设置在n型晶体管的接触开口内，单层衬垫设置在p型晶体管的接触开口内。 n型晶体管和p型晶体管中的接触开口填充有接触材料。 处理单层衬垫以在p型晶体管中形成缺乏镍的硅化物。

公开(公告)号：US20150061032A1

公开(公告)日：2015-03-05

申请号：US14536737

申请日：2014-11-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Derya DENIZ

IPC: H01L29/51 ,  H01L29/78

CPC classification number: H01L29/517 ,  H01L21/283 ,  H01L21/28512 ,  H01L21/28518 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/45 ,  H01L29/456 ,  H01L29/78

Abstract: A semiconductor device with an n-type transistor and a p-type transistor having an active region is provided. The active region further includes two adjacent gate structures. A portion of a dielectric layer between the two adjacent gate structures is selectively removed to form a contact opening having a bottom and sidewalls over the active region. A bilayer liner is selectively provided within the contact opening in the n-type transistor and a monolayer liner is provided within the contact opening in the p-type transistor. The contact opening in the n-type transistor and p-type transistor is filled with contact material. The monolayer liner is treated to form a silicide lacking nickel in the p-type transistor.

Abstract translation: 提供具有n型晶体管和具有有源区的p型晶体管的半导体器件。 有源区还包括两个相邻的门结构。 选择性地去除两个相邻栅极结构之间的介电层的一部分，以形成具有底部和活性区上侧壁的接触开口。 双层衬垫选择性地设置在n型晶体管的接触开口内，单层衬垫设置在p型晶体管的接触开口内。 n型晶体管和p型晶体管中的接触开口填充有接触材料。 处理单层衬垫以在p型晶体管中形成缺乏镍的硅化物。

公开(公告)号：US20140319614A1

公开(公告)日：2014-10-30

申请号：US13870854

申请日：2013-04-25

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Abhijeet PAUL ,  Abner BELLO ,  Vimal K. KAMINENI ,  Derya DENIZ

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/785

Abstract: Performance of a FinFET is enhanced through a structure that exerts physical stress on the channel. The stress is achieved by a combination of tungsten contacts for the source and drain, epitaxially grown raised source and raised drain, and manipulation of aspects of the tungsten contact deposition resulting in enhancement of the inherent stress of tungsten. The stress can further be enhanced by epitaxially re-growing the portion of the raised source and drain removed by etching trenches for the contacts and/or etching deeper trenches (and corresponding longer contacts) below a surface of the fin.

Abstract translation: 通过在通道上施加物理应力的结构来增强FinFET的性能。 应力通过用于源极和漏极的钨触点，外延生长的升高源和升高的漏极的组合以及钨接触沉积的方面的操作来实现，从而导致钨的固有应力的增强。 通过外延重新生长升高的源极和漏极的部分，通过蚀刻用于触点的沟槽和/或蚀刻在鳍的表面下方的较深的沟槽（和相应的更长的触点）来进一步增强应力。