公开(公告)号：US20170221882A1

公开(公告)日：2017-08-03

申请号：US15013411

申请日：2016-02-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ananth Sundaram ,  Balaji Swaminathan ,  Srikumar Konduru ,  Alvin Joseph ,  Michael Zierak

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/528

CPC classification number: H01L27/088 ,  H01L21/823418 ,  H01L21/823475 ,  H01L23/522 ,  H01L23/528 ,  H01L27/0207

Abstract: Chip structures having wiring coupled with the device structures of a high frequency switch and methods for fabricating such chip structures. A transistor is formed that includes a first source/drain region, a second source/drain region, and a first gate electrode having a first width aligned in a first direction. A wiring level is formed that includes a wire coupled with the first source/drain region. The wire has a length aligned in a second direction that is different from the first direction.

公开(公告)号：US09721059B1

公开(公告)日：2017-08-01

申请号：US15002808

申请日：2016-01-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Tamilmani Ethirajan ,  Ashwin Srinivas ,  Ananth Sundaram ,  Janakiraman Viraraghavan

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5022 ,  G06F17/5036 ,  G06F2217/80

Abstract: Disclosed are integrated circuit (IC) design methods, systems and computer program products. During IC design, an electrical netlist with built-in electrical resistance elements (i.e., electrical resistors) is extracted based on an IC design layout. A thermal netlist with built-in thermal resistance elements (i.e., thermal resistors) is automatically extracted based on the electrical netlist. This thermal netlist identifies thermal resistors, external thermal nodes and internal thermal node(s) and does so such that there is one-to-one mapping of the thermal resistors to electrical resistors in the electrical netlist, one-to-one mapping of the external thermal nodes to input, output and power supply nodes in the electrical netlist and one-to-one mapping of the internal thermal node(s) to element(s) (e.g., library and/or customized elements) in the electrical netlist. The electrical and thermal netlists are combined and simulations are performed on the combined electrical-thermal netlist in order to generate a thermal-aware performance model of the IC.

公开(公告)号：US20170212978A1

公开(公告)日：2017-07-27

申请号：US15002808

申请日：2016-01-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Tamilmani Ethirajan ,  Ashwin Srinivas ,  Ananth Sundaram ,  Janakiraman Viraraghavan

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5022 ,  G06F17/5036 ,  G06F2217/80

Abstract: Disclosed are integrated circuit (IC) design methods, systems and computer program products. During IC design, an electrical netlist with built-in electrical resistance elements (i.e., electrical resistors) is extracted based on an IC design layout. A thermal netlist with built-in thermal resistance elements (i.e., thermal resistors) is automatically extracted based on the electrical netlist. This thermal netlist identifies thermal resistors, external thermal nodes and internal thermal node(s) and does so such that there is one-to-one mapping of the thermal resistors to electrical resistors in the electrical netlist, one-to-one mapping of the external thermal nodes to input, output and power supply nodes in the electrical netlist and one-to-one mapping of the internal thermal node(s) to element(s) (e.g., library and/or customized elements) in the electrical netlist. The electrical and thermal netlists are combined and simulations are performed on the combined electrical-thermal netlist in order to generate a thermal-aware performance model of the IC.

公开(公告)号：US09721948B1

公开(公告)日：2017-08-01

申请号：US15013411

申请日：2016-02-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ananth Sundaram ,  Balaji Swaminathan ,  Srikumar Konduru ,  Alvin Joseph ,  Michael Zierak

IPC: H01L27/088 ,  H01L23/528 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/823418 ,  H01L21/823475 ,  H01L23/522 ,  H01L23/528 ,  H01L27/0207

Abstract: Chip structures having wiring coupled with the device structures of a high frequency switch and methods for fabricating such chip structures. A transistor is formed that includes a first source/drain region, a second source/drain region, and a first gate electrode having a first width aligned in a first direction. A wiring level is formed that includes a wire coupled with the first source/drain region. The wire has a length aligned in a second direction that is different from the first direction.