公开(公告)号：US20210066503A1

公开(公告)日：2021-03-04

申请号：US16551794

申请日：2019-08-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anupam Dutta ,  Balaji Swaminathan

IPC: H01L29/786 ,  H01L27/12 ,  G01R31/26 ,  H01L29/10 ,  G06F17/50

Abstract: Test structures for a body-contacted field effect transistor (BCFET) include: a single-pad structure with body contact and probe pad regions connected to a channel region at first and second connection points with a known separation distance between the connection points; and a multi-pad structure with a body contact region connected to a channel region at a first connection point and multiple probe pad regions connected to the channel region at second connection points that are separated from the first connection point by different separation distances. A method includes: determining separation distance-dependent internal body potentials at the second connection points in response to different bias conditions by using either multiple single-pad structures, each having a different separation distance between the connection points, or by using a multi-pad structure; and based on the separation distance-dependent internal body potentials, generating a model representing the BCFET with body-contacted and floating body devices.

公开(公告)号：US09721948B1

公开(公告)日：2017-08-01

申请号：US15013411

申请日：2016-02-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ananth Sundaram ,  Balaji Swaminathan ,  Srikumar Konduru ,  Alvin Joseph ,  Michael Zierak

IPC: H01L27/088 ,  H01L23/528 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/823418 ,  H01L21/823475 ,  H01L23/522 ,  H01L23/528 ,  H01L27/0207

Abstract: Chip structures having wiring coupled with the device structures of a high frequency switch and methods for fabricating such chip structures. A transistor is formed that includes a first source/drain region, a second source/drain region, and a first gate electrode having a first width aligned in a first direction. A wiring level is formed that includes a wire coupled with the first source/drain region. The wire has a length aligned in a second direction that is different from the first direction.

公开(公告)号：US20170221882A1

公开(公告)日：2017-08-03

申请号：US15013411

申请日：2016-02-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ananth Sundaram ,  Balaji Swaminathan ,  Srikumar Konduru ,  Alvin Joseph ,  Michael Zierak

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/528

CPC classification number: H01L27/088 ,  H01L21/823418 ,  H01L21/823475 ,  H01L23/522 ,  H01L23/528 ,  H01L27/0207

Abstract: Chip structures having wiring coupled with the device structures of a high frequency switch and methods for fabricating such chip structures. A transistor is formed that includes a first source/drain region, a second source/drain region, and a first gate electrode having a first width aligned in a first direction. A wiring level is formed that includes a wire coupled with the first source/drain region. The wire has a length aligned in a second direction that is different from the first direction.