公开(公告)号：US10366996B2

公开(公告)日：2019-07-30

申请号：US15704598

申请日：2017-09-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Robert C. Wong ,  Lei Zhuang ,  Ananthan Raghunathan

IPC: H01L27/11 ,  H01L23/31 ,  H01L21/56 ,  H01L21/308 ,  H01L21/3065 ,  H01L27/02

Abstract: Fabrication method for a semiconductor memory device and structure are provided, which includes: providing at least two mask layers over a pair of fin structures extended above a substrate, wherein a first mask layer of the at least two mask layers is orthogonal to a second mask layer of the at least two mask layers; and patterning the pair of fin structures to define a pass-gate transistor, wherein the first mask layer facilitates removing of a portion of a first fin structure of the pair of fin structures to define a first pass-gate fin portion of the pass-gate transistor, and the second mask layer protects a second fin structure of the pair of fin structures to define a second pass-gate fin portion of the pass-gate transistor.

公开(公告)号：US20170352145A1

公开(公告)日：2017-12-07

申请号：US15175101

申请日：2016-06-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Parul Dhagat ,  Ananthan Raghunathan ,  Vikas Sachan ,  Dmitry A. Vengertsev

IPC: G06T7/00 ,  G02B21/00

CPC classification number: G02B21/002 ,  G06T7/0004 ,  G06T2207/10004 ,  G06T2207/10061 ,  G06T2207/20012 ,  G06T2207/20021 ,  G06T2207/30148

Abstract: In the methods and systems, optical images of inspection care areas on a semiconductor wafer are acquired and analyzed to detect defects. However, during this analysis, the same threshold setting is not used for all inspection care areas. Instead, care areas are grouped into different care area groups, based on different design layouts and properties. Each group is associated with a corresponding threshold setting that is optimal for detecting defects in the inspection care areas belonging to that group. The assignment of the care areas to the different groups and the association of the different threshold settings with the different groups are noted in an index. This index is accessible during the analysis and used to ensure that each of the inspection care areas in a specific care area group is analyzed based on a corresponding threshold setting that is optimal for that specific care area group.

公开(公告)号：US10146036B2

公开(公告)日：2018-12-04

申请号：US15175101

申请日：2016-06-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Parul Dhagat ,  Ananthan Raghunathan ,  Vikas Sachan ,  Dmitry A. Vengertsev

IPC: G06T7/00 ,  G02B21/00

Abstract: In the methods and systems, optical images of inspection care areas on a semiconductor wafer are acquired and analyzed to detect defects. However, during this analysis, the same threshold setting is not used for all inspection care areas. Instead, care areas are grouped into different care area groups, based on different design layouts and properties. Each group is associated with a corresponding threshold setting that is optimal for detecting defects in the inspection care areas belonging to that group. The assignment of the care areas to the different groups and the association of the different threshold settings with the different groups are noted in an index. This index is accessible during the analysis and used to ensure that each of the inspection care areas in a specific care area group is analyzed based on a corresponding threshold setting that is optimal for that specific care area group.

公开(公告)号：US09799660B1

公开(公告)日：2017-10-24

申请号：US15151622

申请日：2016-05-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Robert C. Wong ,  Lei Zhuang ,  Ananthan Raghunathan

IPC: H01L27/11 ,  H01L21/56 ,  H01L21/308 ,  H01L21/3065 ,  H01L23/31

CPC classification number: H01L27/1104 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/56 ,  H01L23/3171 ,  H01L27/0207

Abstract: Fabrication method for a semiconductor memory device and structure are provided, which includes: providing at least two mask layers over a pair of fin structures extended above a substrate, wherein a first mask layer of the at least two mask layers is orthogonal to a second mask layer of the at least two mask layers; and patterning the pair of fin structures to define a pass-gate transistor, wherein the first mask layer facilitates removing of a portion of a first fin structure of the pair of fin structures to define a first pass-gate fin portion of the pass-gate transistor, and the second mask layer protects a second fin structure of the pair of fin structures to define a second pass-gate fin portion of the pass-gate transistor.