公开(公告)号：US10366996B2

公开(公告)日：2019-07-30

申请号：US15704598

申请日：2017-09-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Robert C. Wong ,  Lei Zhuang ,  Ananthan Raghunathan

IPC: H01L27/11 ,  H01L23/31 ,  H01L21/56 ,  H01L21/308 ,  H01L21/3065 ,  H01L27/02

Abstract: Fabrication method for a semiconductor memory device and structure are provided, which includes: providing at least two mask layers over a pair of fin structures extended above a substrate, wherein a first mask layer of the at least two mask layers is orthogonal to a second mask layer of the at least two mask layers; and patterning the pair of fin structures to define a pass-gate transistor, wherein the first mask layer facilitates removing of a portion of a first fin structure of the pair of fin structures to define a first pass-gate fin portion of the pass-gate transistor, and the second mask layer protects a second fin structure of the pair of fin structures to define a second pass-gate fin portion of the pass-gate transistor.

公开(公告)号：US09472558B1

公开(公告)日：2016-10-18

申请号：US14940499

申请日：2015-11-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Carl Radens ,  Robert C. Wong

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L27/11 ,  H01L23/528 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/1116 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0688 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848

Abstract: Disclosed are semiconductor structures and methods of forming them. The structures include field effect transistors (FETs) with different type conductivities in different levels, respectively, of the same fin, wherein the numbers of FETs in the different levels are different. Specifically, in a fin, a first semiconductor layer has source/drain and channel regions for a first and a second transistor and a second semiconductor layer has source/drain and channel regions for a third transistor with a different type conductivity than first and second transistors. A gate is on the top surface and sides of the first semiconductor layer at the channel region of the first transistor. Another gate has a lower portion on the sides of the first semiconductor layer at the channel region of the second transistor and an upper portion on the top surface and sides of the second semiconductor layer at the channel region of the third transistor.

Abstract translation: 公开了半导体结构及其形成方法。 该结构分别包括具有不同级别的不同类型电导率的场效应晶体管（FET），其中不同级别的FET的数量是不同的。 具体地，在散热片中，第一半导体层具有用于第一和第二晶体管的源极/漏极和沟道区，并且第二半导体层具有用于具有与第一和第二晶体管不同的导电类型的第三晶体管的源极/漏极和沟道区 。 栅极位于第一晶体管的沟道区的第一半导体层的顶表面和侧面上。 另一个栅极在第二晶体管的沟道区域处具有在第一半导体层的侧面上的下部，在第三晶体管的沟道区域处的第二半导体层的顶部表面和侧面上的上部。

公开(公告)号：US09799660B1

公开(公告)日：2017-10-24

申请号：US15151622

申请日：2016-05-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Robert C. Wong ,  Lei Zhuang ,  Ananthan Raghunathan

IPC: H01L27/11 ,  H01L21/56 ,  H01L21/308 ,  H01L21/3065 ,  H01L23/31

CPC classification number: H01L27/1104 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/56 ,  H01L23/3171 ,  H01L27/0207

Abstract: Fabrication method for a semiconductor memory device and structure are provided, which includes: providing at least two mask layers over a pair of fin structures extended above a substrate, wherein a first mask layer of the at least two mask layers is orthogonal to a second mask layer of the at least two mask layers; and patterning the pair of fin structures to define a pass-gate transistor, wherein the first mask layer facilitates removing of a portion of a first fin structure of the pair of fin structures to define a first pass-gate fin portion of the pass-gate transistor, and the second mask layer protects a second fin structure of the pair of fin structures to define a second pass-gate fin portion of the pass-gate transistor.