公开(公告)号：US10263418B2

公开(公告)日：2019-04-16

申请号：US15971265

申请日：2018-05-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ephrem G. Gebreselasie ,  Icko E. T. Iben ,  Alain Loiseau

IPC: H02H9/04

Abstract: ESD protection circuitry that includes one, or more, of the following features, characteristics and/or advantages: (i) use of different “diode types” (for example, Schottky type, PN type, p-type diode-connected field-effect transistor (FET) type, NFET type)) in a series-connected diode set (connected in series with respect to a device-under-protection) and a parallel-connected diode set (connected in parallel with respect to a device-under-protection and the series-connected diode set); (ii) a FET is connected in series with a target device such that the FET's gate can be turned on during normal operation and the FET's gate is resistively coupled to the FET's source; and/or (iii) two FETs are connected in series with a target device such both FETs gates can be turned on during normal operation, one FET's gate is resistively coupled to its source, and the other FET's gate is electrically coupled to its drain.

公开(公告)号：US20180254630A1

公开(公告)日：2018-09-06

申请号：US15971265

申请日：2018-05-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ephrem G. Gebreselasie ,  Icko E. T. Iben ,  Alain Loiseau

IPC: H02H9/04

CPC classification number: H02H9/041

Abstract: ESD protection circuitry that includes one, or more, of the following features, characteristics and/or advantages: (i) use of different “diode types” (for example, Schottky type, PN type, p-type diode-connected field-effect transistor (FET) type, NFET type)) in a series-connected diode set (connected in series with respect to a device-under-protection) and a parallel-connected diode set (connected in parallel with respect to a device-under-protection and the series-connected diode set); (ii) a FET is connected in series with a target device such that the FET's gate can be turned on during normal operation and the FET's gate is resistively coupled to the FET's source; and/or (iii) two FETs are connected in series with a target device such both FETs gates can be turned on during normal operation, one FET's gate is resistively coupled to its source, and the other FET's gate is electrically coupled to its drain.