公开(公告)号：US10096587B1

公开(公告)日：2018-10-09

申请号：US15794688

申请日：2017-10-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mickey Yu ,  Alain Loiseau ,  Souvick Mitra ,  Tsung-Che Tsai ,  You Li ,  Robert J. Gauthier, Jr.

IPC: H01L27/02 ,  H01L27/088 ,  H01L21/8234 ,  H01L23/535 ,  H01L29/06

Abstract: Diode structures and methods of fabricating diode structures. First and second gate structures are formed with the second gate structure arranged parallel to the first gate structure. First and second fins are formed that extend vertically from a top surface of a substrate. The first and second fins are arranged between the first gate structure and the second gate structure. A contact structure is coupled with the first fin and the second fin. The contact structure is laterally arranged between the first gate structure and the second gate structure.

公开(公告)号：US09318217B1

公开(公告)日：2016-04-19

申请号：US14522017

申请日：2014-10-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ephrem G. Gebreselasie ,  Alain Loiseau ,  Joseph M. Lukaitis ,  Richard A. Poro, III ,  Andreas D. Stricker

IPC: H01H37/76 ,  G11C17/16 ,  H03K19/177 ,  G06F17/50

CPC classification number: G11C17/16 ,  G11C17/18 ,  H03K19/17768

Abstract: Circuits for programming an electrical fuse, methods for programming an electrical fuse, and methods for designing a silicon-controlled rectifier for use in programming an electrical fuse. A programming current for the electrical fuse is directed through the electrical fuse and the silicon-controlled rectifier. Upon reaching a programmed resistance value for the electrical fuse, the silicon-controlled rectifier switches from a low-impedance state to a high-impedance state that interrupts the programming current.

Abstract translation: 用于编程电熔丝的电路，用于编程电熔丝的方法以及用于设计用于编程电熔丝的硅控整流器的方法。 电熔丝的编程电流通过电熔丝和可控硅整流器引导。 当达到电熔丝的编程电阻值时，硅控整流器从低阻抗状态切换到中断编程电流的高阻抗状态。

公开(公告)号：US20200098909A1

公开(公告)日：2020-03-26

申请号：US16137739

申请日：2018-09-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Robert Gauthier, JR. ,  Souvick Mitra ,  Alain Loiseau ,  Tsai Tsung-Che ,  Mickey Yu ,  You Li

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

Abstract: Structures for laterally-diffused metal-oxide-semiconductor devices and drain-extended metal-oxide-semiconductor devices, as well as methods of forming laterally-diffused metal-oxide-semiconductor devices and drain-extended metal-oxide-semiconductor devices. A gate electrode is arranged to extend about a semiconductor fin projecting from a substrate. A drain region is arranged in the substrate, and a source region is coupled with the semiconductor fin. The source region is arranged over the semiconductor fin. A drift region is arranged in the substrate between the drain region and the semiconductor fin. The drain region, source region, and drift region have a given conductivity type. The drift region has a lower electrical conductivity than the drain region.

公开(公告)号：US20160118138A1

公开(公告)日：2016-04-28

申请号：US14522017

申请日：2014-10-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ephrem G. Gebreselasie ,  Alain Loiseau ,  Joseph M. Lukaitis ,  Richard A. Poro, III ,  Andreas D. Stricker

IPC: G11C17/16 ,  G06F17/50 ,  H03K19/177

CPC classification number: G11C17/16 ,  G11C17/18 ,  H03K19/17768

Abstract: Circuits for programming an electrical fuse, methods for programming an electrical fuse, and methods for designing a silicon-controlled rectifier for use in programming an electrical fuse. A programming current for the electrical fuse is directed through the electrical fuse and the silicon-controlled rectifier. Upon reaching a programmed resistance value for the electrical fuse, the silicon-controlled rectifier switches from a low-impedance state to a high-impedance state that interrupts the programming current.

Abstract translation: 用于编程电熔丝的电路，用于编程电熔丝的方法以及用于设计用于编程电熔丝的硅控整流器的方法。 电熔丝的编程电流通过电熔丝和可控硅整流器引导。 当达到电熔丝的编程电阻值时，硅控整流器从低阻抗状态切换到中断编程电流的高阻态。

公开(公告)号：US10692852B2

公开(公告)日：2020-06-23

申请号：US16171760

申请日：2018-10-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alain Loiseau ,  You Li ,  Mickey Yu ,  Tsung-Che Tsai ,  Souvick Mitra ,  Robert J. Gauthier, Jr.

IPC: H01L29/74 ,  H01L27/02 ,  H01L21/762 ,  H01L29/06 ,  H01L29/66

Abstract: Silicon-controlled rectifiers and methods for forming a silicon-controlled rectifier. A first well of a first conductivity type is arranged in a substrate, and second and third wells of a second conductivity type are arranged in the substrate between the first well and the top surface of the substrate. A deep trench isolation region is laterally arranged between the first well of the second conductivity type and the second well of the second conductivity type. The second well is adjoined with the first well along a first interface, the third well is adjoined with the first well along a second interface, and the deep trench isolation region extends the top surface of the substrate past the first interface and the second interface and into the first well. A doped region of the first conductivity type is arranged in the substrate between the second well and the top surface of the substrate.

公开(公告)号：US20200135715A1

公开(公告)日：2020-04-30

申请号：US16171760

申请日：2018-10-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alain Loiseau ,  You Li ,  Mickey Yu ,  Tsung-Che Tsai ,  Souvick Mitra ,  Robert J. Gauthier, JR.

IPC: H01L27/02 ,  H01L29/74 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762

Abstract: Silicon-controlled rectifiers and methods for forming a silicon-controlled rectifier. A first well of a first conductivity type is arranged in a substrate, and second and third wells of a second conductivity type are arranged in the substrate between the first well and the top surface of the substrate. A deep trench isolation region is laterally arranged between the first well of the second conductivity type and the second well of the second conductivity type. The second well is adjoined with the first well along a first interface, the third well is adjoined with the first well along a second interface, and the deep trench isolation region extends the top surface of the substrate past the first interface and the second interface and into the first well. A doped region of the first conductivity type is arranged in the substrate between the second well and the top surface of the substrate.

公开(公告)号：US10290626B1

公开(公告)日：2019-05-14

申请号：US15870238

申请日：2018-01-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： You Li ,  Alain Loiseau ,  Tsung-Che Tsai ,  Mickey Yu ,  Souvick Mitra ,  Robert Gauthier, Jr.

IPC: H01L27/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/285 ,  H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L23/535

Abstract: Methods of integrating a HV ESD PNP bipolar transistor in a VFET process and the resulting devices are provided. Embodiments include forming a DNW region in a portion of a p-sub; forming a HVPDDD region in a portion of the DNW region; forming a first and a second NW in a portion of the DNW region, the second NW between the first NW and the HVPDDD region and laterally separated from the HVPDDD region; forming a PW in a portion of the HVPDDD region; forming an N+ implant in a portion of the first NW and a P+ implant in a portion of the PW; forming a first, a second and a third fin structures over the first and the second NW and the PW, respectively; and forming a N+ S/D, a P+ S/D and a P+ S/D over the first, the second and the third fin structures, respectively.

公开(公告)号：US10263418B2

公开(公告)日：2019-04-16

申请号：US15971265

申请日：2018-05-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ephrem G. Gebreselasie ,  Icko E. T. Iben ,  Alain Loiseau

IPC: H02H9/04

Abstract: ESD protection circuitry that includes one, or more, of the following features, characteristics and/or advantages: (i) use of different “diode types” (for example, Schottky type, PN type, p-type diode-connected field-effect transistor (FET) type, NFET type)) in a series-connected diode set (connected in series with respect to a device-under-protection) and a parallel-connected diode set (connected in parallel with respect to a device-under-protection and the series-connected diode set); (ii) a FET is connected in series with a target device such that the FET's gate can be turned on during normal operation and the FET's gate is resistively coupled to the FET's source; and/or (iii) two FETs are connected in series with a target device such both FETs gates can be turned on during normal operation, one FET's gate is resistively coupled to its source, and the other FET's gate is electrically coupled to its drain.

公开(公告)号：US20180254630A1

公开(公告)日：2018-09-06

申请号：US15971265

申请日：2018-05-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ephrem G. Gebreselasie ,  Icko E. T. Iben ,  Alain Loiseau

IPC: H02H9/04

CPC classification number: H02H9/041

Abstract: ESD protection circuitry that includes one, or more, of the following features, characteristics and/or advantages: (i) use of different “diode types” (for example, Schottky type, PN type, p-type diode-connected field-effect transistor (FET) type, NFET type)) in a series-connected diode set (connected in series with respect to a device-under-protection) and a parallel-connected diode set (connected in parallel with respect to a device-under-protection and the series-connected diode set); (ii) a FET is connected in series with a target device such that the FET's gate can be turned on during normal operation and the FET's gate is resistively coupled to the FET's source; and/or (iii) two FETs are connected in series with a target device such both FETs gates can be turned on during normal operation, one FET's gate is resistively coupled to its source, and the other FET's gate is electrically coupled to its drain.

公开(公告)号：US10741685B2

公开(公告)日：2020-08-11

申请号：US16137739

申请日：2018-09-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Robert Gauthier, Jr. ,  Souvick Mitra ,  Alain Loiseau ,  Tsai Tsung-Che ,  Mickey Yu ,  You Li

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/24

Abstract: Structures for laterally-diffused metal-oxide-semiconductor devices and drain-extended metal-oxide-semiconductor devices, as well as methods of forming laterally-diffused metal-oxide-semiconductor devices and drain-extended metal-oxide-semiconductor devices. A gate electrode is arranged to extend about a semiconductor fin projecting from a substrate. A drain region is arranged in the substrate, and a source region is coupled with the semiconductor fin. The source region is arranged over the semiconductor fin. A drift region is arranged in the substrate between the drain region and the semiconductor fin. The drain region, source region, and drift region have a given conductivity type. The drift region has a lower electrical conductivity than the drain region.