公开(公告)号：US20170162508A1

公开(公告)日：2017-06-08

申请号：US14957860

申请日：2015-12-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mukta G. Farooq ,  Joyce C. Liu ,  Jennifer A. Oakley

IPC: H01L23/538 ,  H01L21/762 ,  H01L21/02 ,  H01L29/06 ,  H01L21/768

CPC classification number: H01L21/762 ,  H01L21/0228 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/481 ,  H01L29/0642

Abstract: Through-substrate vias (TSVs) include a strain engineering layer configured to minimize or otherwise control local stress fields. The strain engineering layer can be separate from and in addition to a TSV sidewall isolation layer that is deposited along the via sidewall surface for the purpose of electric isolation. For instance, the strain engineering layer can be a partial depth layer that extends over only a portion of the TSV sidewall.

公开(公告)号：US09728506B2

公开(公告)日：2017-08-08

申请号：US14957860

申请日：2015-12-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mukta G. Farooq ,  Joyce C. Liu ,  Jennifer A. Oakley

IPC: H01L23/52 ,  H01L23/538 ,  H01L29/06 ,  H01L21/768 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L21/762 ,  H01L21/0228 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/481 ,  H01L29/0642

Abstract: Through-substrate vias (TSVs) include a strain engineering layer configured to minimize or otherwise control local stress fields. The strain engineering layer can be separate from and in addition to a TSV sidewall isolation layer that is deposited along the via sidewall surface for the purpose of electric isolation. For instance, the strain engineering layer can be a partial depth layer that extends over only a portion of the TSV sidewall.

公开(公告)号：US20160379883A1

公开(公告)日：2016-12-29

申请号：US14749843

申请日：2015-06-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mukta G. Farooq ,  Andrew J. Martin ,  Jennifer A. Oakley

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L23/481

Abstract: A method of forming through silicon vias (TSVs) on integrated circuit (IC) chips and the IC chips. A TSV pattern on a stack of wiring layers on the surface of the IC chip identifies TSV locations. Etching the IC chip TSV pattern opens a cup shaped through hole through the stack to the silicon substrate at each TSV pattern location. The etched stack forms a TSV hard mask open (HMO) for the silicon substrate. Via through holes etched through the silicon substrate masked by the HMO are filled with conductor connecting IC circuits, e.g., to signal lines on the bottom of the chip.

Abstract translation: 一种在集成电路（IC）芯片和IC芯片上形成硅通孔（TSV）的方法。 在IC芯片表面上的一层布线层上的TSV图案标识TSV位置。 蚀刻IC芯片TSV图案在每个TSV图案位置处通过堆叠打开杯形通孔到硅衬底。 蚀刻的堆叠形成用于硅衬底的TSV硬掩模开口（HMO）。 蚀刻通过由HMO掩蔽的硅衬底的通孔穿过IC连接IC电路，例如连接到芯片底部的信号线。

公开(公告)号：US09536784B1

公开(公告)日：2017-01-03

申请号：US14749843

申请日：2015-06-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mukta G. Farooq ,  Andrew J. Martin ,  Jennifer A. Oakley

IPC: H01L21/78 ,  H01L21/00 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L23/481

Abstract: A method of forming through silicon vias (TSVs) on integrated circuit (IC) chips and the IC chips. A TSV pattern on a stack of wiring layers on the surface of the IC chip identifies TSV locations. Etching the IC chip TSV pattern opens a cup shaped through hole through the stack to the silicon substrate at each TSV pattern location. The etched stack forms a TSV hard mask open (HMO) for the silicon substrate. Via through holes etched through the silicon substrate masked by the HMO are filled with conductor connecting IC circuits, e.g., to signal lines on the bottom of the chip.

Abstract translation: 一种在集成电路（IC）芯片和IC芯片上形成硅通孔（TSV）的方法。 在IC芯片表面上的一层布线层上的TSV图案标识TSV位置。 蚀刻IC芯片TSV图案在每个TSV图案位置处通过堆叠打开杯形通孔到硅衬底。 蚀刻的堆叠形成用于硅衬底的TSV硬掩模开口（HMO）。 蚀刻通过由HMO掩蔽的硅衬底的通孔穿过IC连接IC电路，例如连接到芯片底部的信号线。