公开(公告)号：US10095115B2

公开(公告)日：2018-10-09

申请号：US15255237

申请日：2016-09-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Christopher B. Shing ,  Joyce C. Liu ,  Richard D. Kaplan ,  Timothy J. Wiltshire ,  Darius Brown

IPC: G03F7/20 ,  G03F7/40 ,  G03F7/32

Abstract: Methods of forming edge etch protection using dual layers of positive-negative tone resists. According to a method, a wafer substrate is provided. A first type resist is deposited on a surface of the wafer substrate. The first type resist is patterned and a resist ring is created around a peripheral edge of the wafer substrate. The resist ring is cured. A second type resist is deposited on the surface of the wafer substrate and the resist ring. The second type resist is different from the first type resist.

公开(公告)号：US09252133B2

公开(公告)日：2016-02-02

申请号：US14487439

申请日：2014-09-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Christopher N. Collins ,  Mukta G. Farooq ,  Troy L. Graves-Abe ,  Joyce C. Liu ,  Gerd Pfeiffer ,  Thuy L. Tran-Quinn

IPC: H01L23/00 ,  H01L25/065 ,  H01L29/32 ,  H01L21/768 ,  H01L23/538

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/5384 ,  H01L29/32 ,  H01L2224/16225 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: The formation of TSVs (through substrate vias) for 3D applications has proven to be defect dependent upon the type of starting semiconductor substrate employed. In addition to the initial formation of TSVs via Bosch processing, backside 3D wafer processing has also shown a defect dependency on substrate type. High yield of TSV formation can be achieved by utilizing a substrate that embodies bulk micro defects (BMD) at a density between 1e4/cc (particles per cubic centimeter) and 1e7/cc and having equivalent diameter less than 55 nm (nanometers).

Abstract translation: 已经证明用于3D应用的TSV（通过衬底通孔）的形成缺陷取决于所采用的起始半导体衬底的类型。 除了通过博世处理初始形成TSV之外，背面3D晶片处理也显示了对衬底类型的缺陷依赖性。 可以通过利用以1e4 / cc（每立方厘米颗粒）和1e7 / cc之间的密度并且具有小于55nm（纳米）的当量直径的体积微观缺陷（BMD）来实现高产率的TSV形成。

公开(公告)号：US20180047807A1

公开(公告)日：2018-02-15

申请号：US15233229

申请日：2016-08-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Herbert L. Ho ,  Byeong Y. Kim ,  Joyce C. Liu

IPC: H01L49/02 ,  H01L21/768 ,  H01L21/285 ,  H01L27/06 ,  H01L23/535 ,  H01L21/02

CPC classification number: H01L28/60 ,  H01L21/02271 ,  H01L27/0629 ,  H01L27/10861 ,  H01L29/945

Abstract: Device structures for a deep trench capacitor and methods of fabricating device structures for a deep trench capacitor. A dielectric layer is formed on a substrate and an opening is formed that extends from a top surface of the dielectric layer through the dielectric layer. A deep trench is formed in the substrate and is aligned with the opening in the dielectric layer. A plate of a deep trench capacitor is formed that is located at least partially inside the deep trench and at least partially inside the opening in the dielectric layer. A diffusion pad is formed that arranged at the top surface of the dielectric layer relative to the opening such that the diffusion pad is coupled with the plate of the deep trench capacitor.

公开(公告)号：US09847290B1

公开(公告)日：2017-12-19

申请号：US15375924

申请日：2016-12-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： John M. Safran ,  Jochonia N. Nxumalo ,  Joyce C. Liu ,  Sami Rosenblatt ,  Chandrasekharan Kothandaraman

IPC: H01L21/768 ,  H01L29/40 ,  H01L29/45 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76807 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/528

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to Through-Silicon Via (TSV) structures with improved substrate contact and methods of manufacture. The structure includes: a substrate of a first species type; a layer of different species type on the substrate; a through substrate via formed through the substrate and comprising an insulator sidewall and conductive fill material; a second species type adjacent the through substrate via; a first contact in electrical contact with the layer of different species type; and a second contact in electrical contact with the conductive fill material of the through substrate via.

公开(公告)号：US20170162508A1

公开(公告)日：2017-06-08

申请号：US14957860

申请日：2015-12-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mukta G. Farooq ,  Joyce C. Liu ,  Jennifer A. Oakley

IPC: H01L23/538 ,  H01L21/762 ,  H01L21/02 ,  H01L29/06 ,  H01L21/768

CPC classification number: H01L21/762 ,  H01L21/0228 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/481 ,  H01L29/0642

Abstract: Through-substrate vias (TSVs) include a strain engineering layer configured to minimize or otherwise control local stress fields. The strain engineering layer can be separate from and in addition to a TSV sidewall isolation layer that is deposited along the via sidewall surface for the purpose of electric isolation. For instance, the strain engineering layer can be a partial depth layer that extends over only a portion of the TSV sidewall.

公开(公告)号：US10446484B2

公开(公告)日：2019-10-15

申请号：US15801501

申请日：2017-11-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： John M. Safran ,  Jochonia N. Nxumalo ,  Joyce C. Liu ,  Sami Rosenblatt ,  Chandrasekharan Kothandaraman

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/48 ,  H01L23/528 ,  H01L23/485

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to Through-Silicon Via (TSV) structures with improved substrate contact and methods of manufacture. The structure includes: a substrate of a first species type; a layer of different species type on the substrate; a through substrate via formed through the substrate and comprising an insulator sidewall and conductive fill material; a second species type adjacent the through substrate via; a first contact in electrical contact with the layer of different species type; and a second contact in electrical contact with the conductive fill material of the through substrate via.

公开(公告)号：US09728506B2

公开(公告)日：2017-08-08

申请号：US14957860

申请日：2015-12-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mukta G. Farooq ,  Joyce C. Liu ,  Jennifer A. Oakley

IPC: H01L23/52 ,  H01L23/538 ,  H01L29/06 ,  H01L21/768 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L21/762 ,  H01L21/0228 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/481 ,  H01L29/0642

Abstract: Through-substrate vias (TSVs) include a strain engineering layer configured to minimize or otherwise control local stress fields. The strain engineering layer can be separate from and in addition to a TSV sidewall isolation layer that is deposited along the via sidewall surface for the purpose of electric isolation. For instance, the strain engineering layer can be a partial depth layer that extends over only a portion of the TSV sidewall.