公开(公告)号：US20150303273A1

公开(公告)日：2015-10-22

申请号：US14258488

申请日：2014-04-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Andy Chih-Hung Wei ,  Xiang Hu ,  Jerome F. Wandell ,  Sandeep Gaan

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L27/0886 ,  H01L21/02488 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Provided are approaches for patterning multiple, dense features in a semiconductor device using a memorization layer. Specifically, an approach includes: patterning a plurality of openings in a memorization layer; forming a gap-fill material within each of the plurality of openings; removing the memorization layer; removing an etch stop layer adjacent the gap-fill material, wherein a portion of the etch stop layer remains beneath the gap-fill material; etching a hardmask to form a set of openings above the set of gate structures, wherein the etch to the hardmask also removes the gap-fill material from atop the remaining portion of the etch stop layer; and etching the semiconductor device to remove the hardmask within each of the set of openings. In one embodiment, a set of dummy S/D contact pillars is then formed over a set of fins of the semiconductor device by etching a dielectric layer selective to the gate structures.

Abstract translation: 提供了使用存储层在半导体器件中图案化多个致密特征的方法。 具体地，一种方法包括：在存储层中图形化多个开口; 在所述多个开口的每一个内形成间隙填充材料; 去除记忆层; 去除邻近间隙填充材料的蚀刻停止层，其中蚀刻停止层的一部分保留在间隙填充材料的下面; 蚀刻硬掩模以在所述一组栅极结构之上形成一组开口，其中对所述硬掩模的蚀刻还从所述蚀刻停止层的剩余部分顶部除去所述间隙填充材料; 并蚀刻半导体器件以去除每组开口内的硬掩模。 在一个实施例中，然后通过蚀刻对栅极结构有选择性的电介质层，在半导体器件的一组鳍片上形成一组虚拟S / D接触柱。

公开(公告)号：US09224842B2

公开(公告)日：2015-12-29

申请号：US14258488

申请日：2014-04-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Andy Chih-Hung Wei ,  Xiang Hu ,  Jerome F. Wandell ,  Sandeep Gaan

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/02488 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Provided are approaches for patterning multiple, dense features in a semiconductor device using a memorization layer. Specifically, an approach includes: patterning a plurality of openings in a memorization layer; forming a gap-fill material within each of the plurality of openings; removing the memorization layer; removing an etch stop layer adjacent the gap-fill material, wherein a portion of the etch stop layer remains beneath the gap-fill material; etching a hardmask to form a set of openings above the set of gate structures, wherein the etch to the hardmask also removes the gap-fill material from atop the remaining portion of the etch stop layer; and etching the semiconductor device to remove the hardmask within each of the set of openings. In one embodiment, a set of dummy S/D contact pillars is then formed over a set of fins of the semiconductor device by etching a dielectric layer selective to the gate structures.

Abstract translation: 提供了使用存储层在半导体器件中图案化多个致密特征的方法。 具体地，一种方法包括：在存储层中图形化多个开口; 在所述多个开口的每一个内形成间隙填充材料; 去除记忆层; 去除邻近间隙填充材料的蚀刻停止层，其中蚀刻停止层的一部分保留在间隙填充材料的下面; 蚀刻硬掩模以在所述一组栅极结构之上形成一组开口，其中对所述硬掩模的蚀刻还从所述蚀刻停止层的剩余部分顶部除去所述间隙填充材料; 并蚀刻半导体器件以去除每组开口内的硬掩模。 在一个实施例中，然后通过蚀刻对栅极结构有选择性的电介质层，在半导体器件的一组鳍片上形成一组虚拟S / D接触柱。

公开(公告)号：US09520395B2

公开(公告)日：2016-12-13

申请号：US14949481

申请日：2015-11-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Andy Wei ,  Xiang Hu ,  Jerome F. Wandell ,  Sandeep Gaan

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L21/02 ,  H01L29/417

CPC classification number: H01L27/0886 ,  H01L21/02488 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Provided are approaches for patterning multiple, dense features in a semiconductor device using a memorization layer. Specifically, an approach includes: patterning a plurality of openings in a memorization layer; forming a gap-fill material within each of the plurality of openings; removing the memorization layer; removing an etch stop layer adjacent the gap-fill material, wherein a portion of the etch stop layer remains beneath the gap-fill material; etching a hardmask to form a set of openings above the set of gate structures, wherein the etch to the hardmask also removes the gap-fill material from atop the remaining portion of the etch stop layer; and etching the semiconductor device to remove the hardmask within each of the set of openings. In one embodiment, a set of dummy S/D contact pillars is then formed over a set of fins of the semiconductor device by etching a dielectric layer selective to the gate structures.

Abstract translation: 提供了使用存储层在半导体器件中图案化多个致密特征的方法。 具体地，一种方法包括：在存储层中图形化多个开口; 在所述多个开口的每一个内形成间隙填充材料; 去除记忆层; 去除邻近间隙填充材料的蚀刻停止层，其中蚀刻停止层的一部分保留在间隙填充材料的下面; 蚀刻硬掩模以在所述一组栅极结构之上形成一组开口，其中对所述硬掩模的蚀刻还从所述蚀刻停止层的剩余部分顶部除去所述间隙填充材料; 并蚀刻半导体器件以去除每组开口内的硬掩模。 在一个实施例中，然后通过蚀刻对栅极结构有选择性的电介质层，在半导体器件的一组鳍片上形成一组虚拟S / D接触柱。

公开(公告)号：US20160079242A1

公开(公告)日：2016-03-17

申请号：US14949481

申请日：2015-11-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： GUILLAUME BOUCHE ,  Andy Wei ,  Xiang Hu ,  Jerome F. Wandell ,  Sandeep Gaan

IPC: H01L27/088 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/02488 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Provided are approaches for patterning multiple, dense features in a semiconductor device using a memorization layer. Specifically, an approach includes: patterning a plurality of openings in a memorization layer; forming a gap-fill material within each of the plurality of openings; removing the memorization layer; removing an etch stop layer adjacent the gap-fill material, wherein a portion of the etch stop layer remains beneath the gap-fill material; etching a hardmask to form a set of openings above the set of gate structures, wherein the etch to the hardmask also removes the gap-fill material from atop the remaining portion of the etch stop layer; and etching the semiconductor device to remove the hardmask within each of the set of openings. In one embodiment, a set of dummy S/D contact pillars is then formed over a set of fins of the semiconductor device by etching a dielectric layer selective to the gate structures.