公开(公告)号：US20160043081A1

公开(公告)日：2016-02-11

申请号：US14918012

申请日：2015-10-20

申请人： GLOBALFOUNDRIES Inc.

发明人： Andy Chih-Hung Wei ,  Dae-han Choi ,  Dae Geun Yang ,  Xiang Hu ,  Mariappan Hariharaputhiran

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/311 ,  H01L29/06 ,  H01L21/308 ,  H01L21/02

CPC分类号： H01L27/0886 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02271 ,  H01L21/0332 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/475 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/785

摘要： Embodiments of the present invention provide methods of removing fin portions from a finFET. At a starting point, a high-K dielectric layer is disposed on a substrate. A fin hardmask and lithography stack is deposited on the high-k dielectric. A fin hardmask is exposed, and a first portion of the fin hardmark is removed. The lithography stack is removed. A second portion of the fin hardmask is removed. Fins are formed. A gap fill dielectric is deposited and recessed.

公开(公告)号：US20150380250A1

公开(公告)日：2015-12-31

申请号：US14318901

申请日：2014-06-30

申请人： GLOBALFOUNDRIES Inc.

发明人： Andy Chih-Hung Wei ,  Guillaume Bouche ,  Gabriel Padron Wells ,  Xiang Hu

IPC分类号： H01L21/28 ,  H01L21/762 ,  H01L23/535 ,  H01L27/088 ,  H01L29/06

CPC分类号： H01L21/28008 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/845 ,  H01L23/535 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the present invention provide an improved structure and method of contact formation. A cap nitride is removed from a gate in a region that is distanced from a fin. This facilitates reduced process steps, allowing the gate and the source/drain regions to be opened in the same process step. Extreme Ultraviolet Lithography (EUVL) may be used to pattern the resist to form the contacts.

摘要翻译： 本发明的实施例提供了改进的接触形成的结构和方法。 在与翅片间隔开的区域中，从栅极去除顶盖氮化物。 这有助于减少处理步骤，允许栅极和源极/漏极区域以相同的工艺步骤打开。 可以使用极紫外光刻（EUVL）来形成抗蚀剂以形成接触。

公开(公告)号：US20150303295A1

公开(公告)日：2015-10-22

申请号：US14258279

申请日：2014-04-22

申请人： GLOBALFOUNDRIES Inc.

发明人： Jing Wan ,  Xiang Hu ,  Jinping Liu ,  Gabriel Padron Wells ,  Andy Chih-Hung Wei ,  Guillaume Bouche ,  Cuiqin Xu

IPC分类号： H01L29/78 ,  H01L29/51 ,  H01L29/66

CPC分类号： H01L29/785 ,  H01L29/41791 ,  H01L29/51 ,  H01L29/66795 ,  H01L2029/7858

摘要： Approaches for forming a set of contact openings in a semiconductor device (e.g., a FinFET device) are provided. Specifically, the semiconductor device includes a set of fins formed in a substrate, a gate structure (e.g., replacement metal gate (RMG)) formed over the substrate, and a set of contact openings adjacent the gate structure, each of the set of contact openings having a top section and a bottom section, wherein a width of the bottom section, along a length of the gate structure, is greater than a width of the top section. The semiconductor device further includes a set of metal contacts formed within the set of contact openings.

摘要翻译： 提供了在半导体器件（例如，FinFET器件）中形成一组接触开口的方法。 具体地，半导体器件包括形成在衬底中的一组翅片，形成在衬底上的栅极结构（例如，替换金属栅极（RMG））以及与栅极结构相邻的一组接触开口，该组接触 具有顶部和底部的开口，其中沿着栅极结构的长度的底部的宽度大于顶部的宽度。 半导体器件还包括形成在该组接触开口内的一组金属触头。

公开(公告)号：US20150303273A1

公开(公告)日：2015-10-22

申请号：US14258488

申请日：2014-04-22

申请人： GLOBALFOUNDRIES Inc.

发明人： Guillaume Bouche ,  Andy Chih-Hung Wei ,  Xiang Hu ,  Jerome F. Wandell ,  Sandeep Gaan

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/02

CPC分类号： H01L27/0886 ,  H01L21/02488 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

摘要： Provided are approaches for patterning multiple, dense features in a semiconductor device using a memorization layer. Specifically, an approach includes: patterning a plurality of openings in a memorization layer; forming a gap-fill material within each of the plurality of openings; removing the memorization layer; removing an etch stop layer adjacent the gap-fill material, wherein a portion of the etch stop layer remains beneath the gap-fill material; etching a hardmask to form a set of openings above the set of gate structures, wherein the etch to the hardmask also removes the gap-fill material from atop the remaining portion of the etch stop layer; and etching the semiconductor device to remove the hardmask within each of the set of openings. In one embodiment, a set of dummy S/D contact pillars is then formed over a set of fins of the semiconductor device by etching a dielectric layer selective to the gate structures.

摘要翻译： 提供了使用存储层在半导体器件中图案化多个致密特征的方法。 具体地，一种方法包括：在存储层中图形化多个开口; 在所述多个开口的每一个内形成间隙填充材料; 去除记忆层; 去除邻近间隙填充材料的蚀刻停止层，其中蚀刻停止层的一部分保留在间隙填充材料的下面; 蚀刻硬掩模以在所述一组栅极结构之上形成一组开口，其中对所述硬掩模的蚀刻还从所述蚀刻停止层的剩余部分顶部除去所述间隙填充材料; 并蚀刻半导体器件以去除每组开口内的硬掩模。 在一个实施例中，然后通过蚀刻对栅极结构有选择性的电介质层，在半导体器件的一组鳍片上形成一组虚拟S / D接触柱。

公开(公告)号：US09034767B1

公开(公告)日：2015-05-19

申请号：US14076386

申请日：2013-11-11

申请人： GLOBALFOUNDRIES Inc.

发明人： Xiang Hu ,  Dae-Han Choi ,  Dae Geun Yang ,  Taejoon Han ,  Andy Wei

IPC分类号： H01L21/311 ,  H01L21/30 ,  H01L21/308

CPC分类号： H01L21/0337

摘要： Mask pattern formation is facilitated by: providing a mask structure including at least one sacrificial spacing structure disposed above a substrate structure; disposing a spacer layer conformally over the mask structure; selectively removing the spacer layer, leaving, at least in part, sidewall spacers along sidewalls of the at least one sacrificial spacing structure, and providing at least one additional sacrificial spacer over the substrate structure, one additional sacrificial spacer of the at least one additional sacrificial spacer being disposed in set spaced relation to the at least one sacrificial spacing structure; and removing the at least one sacrificial spacing structure, leaving the sidewall spacers and the at least one additional sacrificial spacer over the substrate structure as part of a mask pattern.

摘要翻译： 通过以下方式促进掩模图案形成：提供掩模结构，其包括设置在基板结构上方的至少一个牺牲间隔结构; 将掩模层保形地设置在掩模结构上; 选择性地去除间隔层，至少部分地留下沿着至少一个牺牲间隔结构的侧壁的侧壁间隔物，并且在衬底结构上方提供至少一个额外的牺牲间隔物，该至少一个额外的牺牲隔离物 间隔件与所述至少一个牺牲间隔结构设置成间隔开的关系; 以及去除所述至少一个牺牲间隔结构，将所述侧壁间隔物和所述至少一个另外的牺牲隔离物留在所述衬底结构上作为掩模图案的一部分。

公开(公告)号：US08940641B1

公开(公告)日：2015-01-27

申请号：US14019155

申请日：2013-09-05

申请人： GLOBALFOUNDRIES, Inc.

发明人： Xiang Hu ,  Taejoon Han ,  Hui Peng Koh

IPC分类号： H01L21/311 ,  H01L21/308

CPC分类号： H01L21/31144 ,  H01L21/76816

摘要： Methods for fabricating integrated circuits with improved patterning schemes are provided. In an embodiment, a method for fabricating an integrated circuit includes depositing an interlayer dielectric material overlying a semiconductor substrate. Further, the method includes forming a patterned hard mask overlying the interlayer dielectric material. Also, the method forms an organic planarization layer overlying the patterned hard mask and contacting portions of the interlayer dielectric material. The method patterns the organic planarization layer using an extreme ultraviolet (EUV) lithography process. The method also includes etching the interlayer dielectric material using the patterned hard mask and organic planarization layer as a mask to form vias in the interlayer dielectric material.

摘要翻译： 提供了具有改进的图案化方案的集成电路制造方法。 在一个实施例中，一种用于制造集成电路的方法包括沉积覆盖在半导体衬底上的层间电介质材料。 此外，该方法包括形成覆盖层间电介质材料的图案化硬掩模。 此外，该方法形成覆盖图案化的硬掩模和接触层间电介质材料的部分的有机平坦化层。 该方法使用极紫外（EUV）光刻工艺对有机平面化层进行图案化。 该方法还包括使用图案化硬掩模和有机平坦化层作为掩模蚀刻层间电介质材料，以在层间电介质材料中形成通路。

公开(公告)号：US08835292B2

公开(公告)日：2014-09-16

申请号：US13664744

申请日：2012-10-31

申请人： International Business Machines Corporation ,  Globalfoundries Inc.

发明人： Michael P. Chudzik ,  Min Dai ,  Xiang Hu ,  Jinping Liu ,  Yanxiang Liu ,  Xiaodong Yang

IPC分类号： H01L21/3205

CPC分类号： H01L29/66545 ,  H01L21/2807 ,  H01L21/28088 ,  H01L21/823437 ,  H01L21/823462

摘要： A method of manufacturing a semiconductor device including a replacement metal gate process incorporating a conductive dummy gate layer (e.g., silicon germanium (SiGe), titanium nitride, etc.) and a related are disclosed. The method includes forming an oxide layer on a substrate; removing a gate portion of the oxide layer from the substrate in a first region of the semiconductor device; forming a conductive dummy gate layer on the semiconductor device in the first region; and forming a gate on the semiconductor device, the gate including a gate conductor disposed in the first region and directly connected to the substrate.

摘要翻译： 公开了一种制造半导体器件的方法，该半导体器件包括结合导电虚拟栅极层（例如硅锗（SiGe），氮化钛等）的替代金属栅极工艺）和相关的方法。 该方法包括在衬底上形成氧化物层; 在所述半导体器件的第一区域中从所述衬底去除所述氧化物层的栅极部分; 在所述第一区域中的所述半导体器件上形成导电虚拟栅极层; 以及在所述半导体器件上形成栅极，所述栅极包括设置在所述第一区域中并直接连接到所述衬底的栅极导体。

公开(公告)号：US10121711B2

公开(公告)日：2018-11-06

申请号：US14816708

申请日：2015-08-03

申请人： GLOBALFOUNDRIES Inc.

发明人： Sipeng Gu ,  Xiang Hu ,  Alok Vaid ,  Lokesh Subramany ,  Akshey Sehgal

IPC分类号： H01L29/10 ,  H01L29/76 ,  H01L21/82 ,  H01L21/66 ,  G01R31/26 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092

摘要： Approaches for providing a substrate having a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. Specifically, the FinFET device comprises a finned substrate, and a planar metrology pad formed on the substrate adjacent the fins in a metrology measurement area of the FinFET device. Processing steps include forming a first hardmask over the substrate, forming a photoresist over a portion of the first hardmask in the metrology measurement area of the FinFET device, removing the first hardmask in an area adjacent the metrology measurement area remaining exposed following formation of the photoresist, patterning a set of openings in the substrate to form the set of fins in the FinFET device in the area adjacent the metrology measurement area, depositing an oxide layer over the FinFET device, and planarizing the FinFET device to form the planar metrology pad in the metrology measurement area.

公开(公告)号：US09817927B2

公开(公告)日：2017-11-14

申请号：US14841037

申请日：2015-08-31

申请人： GLOBALFOUNDRIES Inc.

发明人： Guo Xiang Ning ,  Yuping Ren ,  David Power ,  Lalit Shokeen ,  Chin Teong Lim ,  Paul W. Ackmann ,  Xiang Hu

IPC分类号： G06F17/50 ,  G03F1/36

CPC分类号： G06F17/5009 ,  G03F1/36 ,  G06F17/5081

摘要： A method and apparatus for generating a final dielectric etch compensation table and a final hard mask etch compensation table for either OPC or MPC process flows are provided. Embodiments include performing an overlap pattern classification on a wafer; calibrating a dielectric etch bias or a hard mask etch bias based on the pattern classification; comparing either a CD overlap of a via layer with a metal layer and a CD overlap of the via layer with a lower connecting metal layer or a CD overlap of the metal layer with an upper connecting via layer and a CD overlap of the metal layer with the via layer against a criteria; outputting final dielectric etch compensation and hard mask etch compensation tables to either OPC or MPC process flows; and repeating the steps of calibrating, comparing, and outputting for either the via layer or metal layer remaining.

公开(公告)号：US09460963B2

公开(公告)日：2016-10-04

申请号：US14225529

申请日：2014-03-26

申请人： GLOBALFOUNDRIES Inc.

发明人： Gabriel Padron Wells ,  Xiang Hu ,  Guillaume Bouche ,  Andre Labonte

IPC分类号： H01L21/467 ,  H01L21/768 ,  H01L29/40 ,  H01L21/033 ,  H01L21/308 ,  H01L29/417 ,  H01L27/088 ,  H01L21/8234

CPC分类号： H01L21/76897 ,  H01L21/0332 ,  H01L21/3081 ,  H01L21/467 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66795

摘要： Embodiments of the present invention provide an improved contact and method of fabrication. A dielectric layer is formed over transistor structures which include gates and source/drain regions. A first etch, which may be a reactive ion etch, is used to partially recess the dielectric layer. A second etch is then used to continue the etch of the dielectric layer to form a cavity adjacent to the gate spacers. The second etch is highly selective to the spacer material, which prevents damage to the spacers during the exposure (opening) of the source/drain regions.

摘要翻译： 本发明的实施例提供了改进的接触和制造方法。 在包括栅极和源极/漏极区域的晶体管结构上形成介电层。 使用可以是反应离子蚀刻的第一蚀刻来部分地凹陷介电层。 然后使用第二蚀刻来继续蚀刻介电层以形成与栅极间隔物相邻的空腔。 第二蚀刻对间隔物材料具有高选择性，这防止了在源极/漏极区域的曝光（打开）期间损坏间隔物。