公开(公告)号：US12087868B2

公开(公告)日：2024-09-10

申请号：US17629343

申请日：2019-09-11

Applicant: SOUTH CHINA NORMAL UNIVERSITY

Inventor： Richard Notzel

IPC: H01L29/885 ,  H01L21/02 ,  H01L29/20 ,  H01L29/66 ,  H02M7/06

CPC classification number: H01L29/885 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02488 ,  H01L21/0254 ,  H01L21/02631 ,  H01L29/2003 ,  H01L29/66204 ,  H02M7/06

Abstract: An epitaxial wafer, a method of manufacturing the epitaxial wafer, a diode, and a current rectifier are provided. The epitaxial wafer comprises a Si substrate layer; an insulating layer formed on the Si substrate layer; and a nitride semiconductor layer formed on a surface of the insulating layer facing away from the Si substrate layer; wherein the insulating layer has a thickness configured such that under a forward bias voltage, the insulating layer may allow electrons and holes to pass from one side to the other side of the insulating layer via quantum tunneling so as to allow a forward current flow.

公开(公告)号：US20240266184A1

公开(公告)日：2024-08-08

申请号：US18105336

申请日：2023-02-03

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： HSUAN-WU LAI

IPC: H01L21/311 ,  H01L21/02

CPC classification number: H01L21/31122 ,  H01L21/0243 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/02115 ,  H01L21/02271 ,  H01L21/02592 ,  H01L21/02595

Abstract: A method of manufacturing a semiconductor structure is provided. The method includes providing a semiconductor wafer having a central region and a bevel region; forming a first material layer over the central region and the bevel region of the semiconductor wafer; performing a dry etching operation on a portion of the first material layer over the bevel region of the semiconductor wafer; performing a wet etching operation on the portion of the first material layer over the bevel region of the semiconductor wafer; performing a baking operation on the bevel region of the semiconductor wafer; and forming a second material layer on the central region and the bevel region of the semiconductor wafer after performing the baking operation.

公开(公告)号：US12037677B2

公开(公告)日：2024-07-16

申请号：US17204493

申请日：2021-03-17

Applicant: KOKUSAI ELECTRIC CORPORATION

Inventor： Ryuji Yamamoto ,  Yoshiro Hirose

IPC: C23C16/455 ,  C23C16/02 ,  C23C16/24 ,  H01L21/02

CPC classification number: C23C16/02 ,  C23C16/24 ,  C23C16/45542 ,  C23C16/45546 ,  C23C16/45557 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/0262

Abstract: A method of manufacturing a semiconductor device includes forming a seed layer containing a predetermined element on a substrate by performing a process a predetermined number of times, and supplying a second precursor containing the predetermined element and not containing the ligand to the substrate to form a film containing the predetermined element on the seed layer. The process includes alternately performing: supplying a first precursor to the substrate to form an adsorption layer of the first precursor, the first precursor containing the predetermined element and a ligand which is coordinated to the predetermined element and which contains at least one of carbon or nitrogen, and supplying a ligand desorption material to the substrate to desorb the ligand from the adsorption layer of the first precursor.

公开(公告)号：US12034080B2

公开(公告)日：2024-07-09

申请号：US16520831

申请日：2019-07-24

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Junichi Koezuka ,  Kenichi Okazaki ,  Yasuharu Hosaka ,  Masami Jintyou ,  Takahiro Iguchi ,  Shunpei Yamazaki

IPC: H01L29/786 ,  H01L21/02 ,  H01L27/12 ,  H01L29/04 ,  H01L29/24 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L21/02422 ,  H01L21/02488 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/0262 ,  H01L21/02631 ,  H01L27/1225 ,  H01L27/127 ,  H01L29/045 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78696

Abstract: To suppress a change in electrical characteristics in a transistor including an oxide semiconductor film. The transistor includes a first gate electrode, a first insulating film, an oxide semiconductor film, a source electrode, a drain electrode, a second insulating film, a second gate electrode, and a third insulating film. The oxide semiconductor film includes a first oxide semiconductor film on the first gate electrode side, and a second oxide semiconductor film over the first oxide semiconductor film. The first oxide semiconductor film and the second oxide semiconductor film include In, M, and Zn (M is Al, Ga, Y, or Sn). In a region of the second oxide semiconductor film, the number of atoms of In is smaller than that in the first oxide semiconductor film. The second gate electrode includes at least one metal element included in the oxide semiconductor film.

公开(公告)号：US20240128079A1

公开(公告)日：2024-04-18

申请号：US18277360

申请日：2022-02-15

Applicant: Paragraf Limited

Inventor： Ivor GUINEY ,  Sebastian DIXON ,  Jaspreet KAINTH ,  Thomas James BADCOCK ,  Ross Matthew GRIFFIN

IPC: H01L21/02 ,  H01L29/16

CPC classification number: H01L21/02527 ,  H01L21/02381 ,  H01L21/02488 ,  H01L29/1606

Abstract: A method for the manufacture of an improved graphene substrate and applications therefor There is provided a method (100) for the manufacture of an electronic device precursor, the method comprising: (i) providing a silicon wafer (200) having a growth surface (205); (ii) forming (105) an insulative layer (210) on the growth surface (205) having a thickness of from 1 nm to 10 nm, preferably 2 nm to 1 nm; (iii) forming (110) a graphene monolayer or multi-layer structure (215) on the insulative layer (210); (iv) optionally forming (115, 120) one or more further layers (220) and/or electrical contacts (225, 230) on the graphene monolayer or multi-layer structure (215); (v) forming (125) a polymer coating (235) over the graphene monolayer or multi-layer structure (215) and any further layers (115) and/or electrical contacts (225, 230); (vi) thinning (130) the silicon wafer (200), or removing the silicon wafer (200) to provide an exposed surface of the insulative layer (210), by etching with an etchant, wherein the silicon wafer (200) is optionally subjected to a grinding step before etching; and (vii) optionally dissolving away (135) the polymer coating (235); wherein the insulative layer (210) and the polymer coating (235) are resistant to etching by the etchant. The resulting conductive graphene substrate can be used in (organic) LEDs, capacitor devices, tunnel FETs and Hall sensors.

公开(公告)号：US11942363B2

公开(公告)日：2024-03-26

申请号：US17818608

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Kuei-Yu Kao ,  Chen-Ping Chen ,  Chih-Han Lin

IPC: H01L21/76 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/02

CPC classification number: H01L21/76831 ,  H01L21/30608 ,  H01L21/30655 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L21/02236 ,  H01L21/02247 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/3065

Abstract: A method includes etching a semiconductor substrate to form a trench, with the semiconductor substrate having a sidewall facing the trench, and depositing a first semiconductor layer extending into the trench. The first semiconductor layer includes a first bottom portion at a bottom of the trench, and a first sidewall portion on the sidewall of the semiconductor substrate. The first sidewall portion is removed to reveal the sidewall of the semiconductor substrate. The method further includes depositing a second semiconductor layer extending into the trench, with the second semiconductor layer having a second bottom portion over the first bottom portion, and a second sidewall portion contacting the sidewall of the semiconductor substrate. The second sidewall portion is removed to reveal the sidewall of the semiconductor substrate.

公开(公告)号：US11935962B2

公开(公告)日：2024-03-19

申请号：US17744812

申请日：2022-05-16

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Junichi Koezuka ,  Masami Jintyou ,  Yukinori Shima

IPC: H01L29/786 ,  H01L21/02 ,  H01L27/12 ,  H01L29/66 ,  G02F1/1368 ,  H10K59/121

CPC classification number: H01L29/7869 ,  H01L21/02488 ,  H01L21/02513 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/1225 ,  H01L27/127 ,  H01L29/66969 ,  H01L29/78603 ,  G02F1/1368 ,  H10K59/1213

Abstract: A semiconductor device having favorable characteristics is provided. A semiconductor device having stable electrical characteristics is provided. An island-shaped insulating layer containing an oxide is provided in contact with a bottom surface of a semiconductor layer containing a metal oxide that exhibits semiconductor characteristics. The insulating layer containing an oxide is provided in contact with a portion of the semiconductor layer to be a channel formation region and is not provided under portions to be low-resistance regions.

公开(公告)号：USRE49869E1

公开(公告)日：2024-03-12

申请号：US17214607

申请日：2021-03-26

Applicant: iBeam Materials, Inc.

Inventor： Vladimir Matias ,  Christopher Yung

IPC: H01L33/32 ,  H01L21/02 ,  H01L31/00 ,  H01L31/036 ,  H01L33/00 ,  H01L33/18 ,  H01L33/64 ,  H01L33/12 ,  H01L33/60

CPC classification number: H01L33/32 ,  H01L21/02425 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02516 ,  H01L21/0254 ,  H01L21/0262 ,  H01L31/00 ,  H01L31/036 ,  H01L33/007 ,  H01L33/18 ,  H01L33/644 ,  H01L33/12 ,  H01L33/60

Abstract: A multilayer structure including a hexagonal epitaxial layer, such as GaN or other group III-nitride (III-N) semiconductors, a oriented textured layer, and a non-single crystal substrate, and methods for making the same. The textured layer has a crystalline alignment preferably formed by the ion-beam assisted deposition (IBAD) texturing process and can be biaxially aligned. The in-plane crystalline texture of the textured layer is sufficiently low to allow growth of high quality hexagonal material, but can still be significantly greater than the required in-plane crystalline texture of the hexagonal material. The IBAD process enables low-cost, large-area, flexible metal foil substrates to be used as potential alternatives to single-crystal sapphire and silicon for manufacture of electronic devices, enabling scaled-up roll-to-roll, sheet-to-sheet, or similar fabrication processes to be used. The user is able to choose a substrate for its mechanical and thermal properties, such as how well its coefficient of thermal expansion matches that of the hexagonal epitaxial layer, while choosing a textured layer that more closely lattice matches that layer. Electronic devices such as LEDs can be manufactured from such structures. Because the substrate can act as both a reflector and a heat sink, transfer to other substrates, and use of external reflectors and heat sinks, is not required, greatly reducing costs. Large area devices such as light emitting strips or sheets may be fabricated using this technology.

公开(公告)号：US20240063027A1

公开(公告)日：2024-02-22

申请号：US18269646

申请日：2021-12-06

Applicant: SHIN-ETSU HANDOTAI CO., LTD.

Inventor： Katsuyoshi SUZUKI

IPC: H01L21/322 ,  H01L21/02

CPC classification number: H01L21/3221 ,  H01L21/02661 ,  H01L21/02488 ,  H01L21/02532

Abstract: The present invention is a method for producing an epitaxial wafer forming a single crystal silicon layer on a single crystal silicon wafer, comprising, a step of removing native oxide film on surface of the single crystal silicon wafer with hydrofluoric acid, a step of forming an oxygen atomic layer on the surface of the single crystal silicon wafer from which the native oxide film has been removed, a step of epitaxially growing the single crystal silicon layer on the surface of the single crystal silicon wafer on which the oxygen atomic layer is formed, wherein the plane concentration of oxygen in the oxygen atomic layer is 1×1015 atoms/cm2 or less. As a result, a method for producing an epitaxial wafer, that an oxygen atomic layer can be stably and simply introduced into an epitaxial layer, and having a good-quality single crystal silicon epitaxial layer is provided.

公开(公告)号：US20240063021A1

公开(公告)日：2024-02-22

申请号：US18498756

申请日：2023-10-31

Applicant: AKHAN Semiconductor, Inc.

Inventor： Adam Khan

IPC: H01L21/04 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/868 ,  H01L31/028 ,  H01L33/34

CPC classification number: H01L21/0415 ,  H01L21/02085 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/02444 ,  H01L21/02488 ,  H01L21/02527 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/043 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/1602 ,  H01L29/6603 ,  H01L29/66045 ,  H01L29/78 ,  H01L29/868 ,  H01L31/028 ,  H01L33/34 ,  H01L33/005

Abstract: Disclosed herein is a new and improved system and method for fabricating diamond films by first seeding a surface of a transparent substrate. A diamond layer that is at least one of nanocrystalline and ultrananocrystalline can be deposited upon the surface of the transparent substrate and both the diamond layer and the transparent substrate modified to incorporate substitutional atoms.