公开(公告)号：US09367348B2

公开(公告)日：2016-06-14

申请号：US13967853

申请日：2013-08-15

Applicant: GLOBALFOUNDRIES INC

Inventor： Sanjeev Ghai ,  Guy L. Guthrie ,  Jonathan R. Jackson ,  Derek E. Williams

IPC: G06F12/12 ,  G06F9/46 ,  G06F12/08

CPC classification number: G06F9/467 ,  G06F12/0802 ,  G06F12/0815 ,  G06F12/0864 ,  G06F12/123

Abstract: A processing unit includes a processor core and a cache memory. Entries in the cache memory are grouped in multiple congruence classes. The cache memory includes tracking logic that tracks a transaction footprint including cache line(s) accessed by transactional memory access request(s) of a memory transaction. The cache memory, responsive to receiving a memory access request that specifies a target cache line having a target address that maps to a congruence class, forms a working set of ways in the congruence class containing cache line(s) within the transaction footprint and updates a replacement order of the cache lines in the congruence class. Based on membership of the at least one cache line in the working set, the update promotes at least one cache line that is not the target cache line to a replacement order position in which the at least one cache line is less likely to be replaced.

Abstract translation: 处理单元包括处理器核和高速缓冲存储器。 高速缓冲存储器中的条目被分组在多个同余类中。 高速缓冲存储器包括跟踪逻辑，其跟踪事务占用，包括由存储器事务的事务存储器访问请求访问的高速缓存行。 高速缓冲存储器响应于接收指定具有映射到同余类的目标地址的目标高速缓存行的存储器访问请求，形成包含事务占用空间内的高速缓存行的一致性类中的一组工作方式，并更新 一致类中缓存行的替换顺序。 基于工作集中的至少一个高速缓存行的成员身份，该更新将至少一个不是目标高速缓存行的高速缓存行促进到其中至少一个高速缓存行不太可能被替换的替换顺序位置。

公开(公告)号：US09244725B2

公开(公告)日：2016-01-26

申请号：US14037923

申请日：2013-09-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sanjeev Ghai ,  Guy L. Guthrie ,  Jonathan R. Jackson ,  Derek E. Williams

IPC: G06F9/46 ,  G06F12/08

CPC classification number: G06F9/467 ,  G06F12/0802 ,  G06F12/0815 ,  G06F12/0828

Abstract: In a data processing system having a processor core and a shared memory system including a cache memory that supports the processor core, a transactional memory access request is issued by the processor core in response to execution of a memory access instruction in a memory transaction undergoing execution by the processor core. In response to receiving the transactional memory access request, dispatch logic of the cache memory evaluates the transactional memory access request for dispatch, where the evaluation includes determining whether the memory transaction has a failing transaction state. In response to determining the memory transaction has a failing transaction state, the dispatch logic refrains from dispatching the memory access request for service by the cache memory and refrains from updating at least replacement order information of the cache memory in response to the transactional memory access request.

Abstract translation: 在具有处理器核心和包括支持处理器核心的高速缓冲存储器的共享存储器系统的数据处理系统中，处理器核心响应于执行正在执行的存储器事务中的存储器访问指令执行事务存储器访问请求 由处理器核心。 响应于接收事务存储器访问请求，缓存存储器的调度逻辑评估用于调度的事务存储器访问请求，其中评估包括确定存储器事务是否具有故障事务状态。 响应于确定存储器事务具有失败的事务状态，分派逻辑不会缓存高速缓冲存储器的服务存储器访问请求，并且至少响应于事务存储器访问请求更新缓存存储器的替换顺序信息 。

公开(公告)号：US09244724B2

公开(公告)日：2016-01-26

申请号：US13967795

申请日：2013-08-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sanjeev Ghai ,  Guy L. Guthrie ,  Jonathan R. Jackson ,  Derek E. Williams

IPC: G06F9/46 ,  G06F12/08

CPC classification number: G06F9/467 ,  G06F12/0802 ,  G06F12/0815 ,  G06F12/0828

Abstract: In a data processing system having a processor core and a shared memory system including a cache memory that supports the processor core, a transactional memory access request is issued by the processor core in response to execution of a memory access instruction in a memory transaction undergoing execution by the processor core. In response to receiving the transactional memory access request, dispatch logic of the cache memory evaluates the transactional memory access request for dispatch, where the evaluation includes determining whether the memory transaction has a failing transaction state. In response to determining the memory transaction has a failing transaction state, the dispatch logic refrains from dispatching the memory access request for service by the cache memory and refrains from updating at least replacement order information of the cache memory in response to the transactional memory access request.