公开(公告)号：US10510675B2

公开(公告)日：2019-12-17

申请号：US15888366

申请日：2018-02-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Somnath Ghosh ,  Eswar Ramanathan ,  Qanit Takmeel ,  Ming He ,  Jeric Sarad ,  Ashwini Chandrashekar ,  Colin Bombardier ,  Anbu Selvam KM Mahalingam ,  Keith P. Donegan ,  Prakash Periasamy

IPC: H01L21/00 ,  H01L23/544 ,  G01N21/552 ,  G01B11/27 ,  H01L21/68

Abstract: Embodiments of the disclosure provide a substrate structure for an integrated circuit (IC) structure, including: a first dielectric layer positioned above a semiconductor substrate; a first plurality of trenches extending at least partially into the first dielectric layer from an upper surface of the first dielectric layer; and a first metal formed within the first plurality of trenches, wherein a spatial arrangement of the first plurality of trenches causes coupling of surface plasmons in the first metal to at least one wavelength of an incident light.

公开(公告)号：US10566231B2

公开(公告)日：2020-02-18

申请号：US15966032

申请日：2018-04-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Martin J. O'Toole ,  Christopher J. Penny ,  Jae O. Choo ,  Adam L. da Silva ,  Craig Child ,  Terry A. Spooner ,  Hsueh-Chung Chen ,  Brendan O'Brien ,  Keith P. Donegan

IPC: H01L21/768 ,  H01L23/532

Abstract: Methods of forming an interconnect of an IC are disclosed. The methods include forming a first interlayer dielectric (ILD) layer and a second ILD layer with an ILD etch stop layer (ESL) therebetween. The ILD ESL has an etch rate that is at least five times slower than the first and second ILD layers, and may include, for example, aluminum oxynitride. A dual damascene (DD) hard mask is used to form a wire trench opening in the second ILD layer and a via opening in the first ILD layer, creating a via-wire opening. Due to the slower etch rate, the ILD ESL defines the via opening in the first ILD layer as a chamferless via opening. A unitary via-wire conductive structure coupled to the conductive structure in the via-wire opening can be formed from the via-wire opening.

公开(公告)号：US20190333805A1

公开(公告)日：2019-10-31

申请号：US15966032

申请日：2018-04-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Martin J. O'Toole ,  Christopher J. Penny ,  Jae O. Choo ,  Adam L. da Silva ,  Craig Child ,  Terry A. Spooner ,  Hsueh-Chung Chen ,  Brendan O'Brien ,  Keith P. Donegan

IPC: H01L21/768

Abstract: Methods of forming an interconnect of an IC are disclosed. The methods include forming a first interlayer dielectric (ILD) layer and a second ILD layer with an ILD etch stop layer (ESL) therebetween. The ILD ESL has an etch rate that is at least five times slower than the first and second ILD layers, and may include, for example, aluminum oxynitride. A dual damascene (DD) hard mask is used to form a wire trench opening in the second ILD layer and a via opening in the first ILD layer, creating a via-wire opening. Due to the slower etch rate, the ILD ESL defines the via opening in the first ILD layer as a chamferless via opening. A unitary via-wire conductive structure coupled to the conductive structure in the via-wire opening can be formed from the via-wire opening.

公开(公告)号：US20190244911A1

公开(公告)日：2019-08-08

申请号：US15888366

申请日：2018-02-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Somnath Ghosh ,  Eswar Ramanathan ,  Qanit Takmeel ,  Ming He ,  Jeric Sarad ,  Ashwini Chandrashekar ,  Colin Bombardier ,  Anbu Selvam KM Mahalingam ,  Keith P. Donegan ,  Prakash Periasamy

IPC: H01L23/544 ,  H01L21/68 ,  G01B11/27 ,  G01N21/552

Abstract: Embodiments of the disclosure provide a substrate structure for an integrated circuit (IC) structure, including: a first dielectric layer positioned above a semiconductor substrate; a first plurality of trenches extending at least partially into the first dielectric layer from an upper surface of the first dielectric layer; and a first metal formed within the first plurality of trenches, wherein a spatial arrangement of the first plurality of trenches causes coupling of surface plasmons in the first metal to at least one wavelength of an incident light.