公开(公告)号：US20190244911A1

公开(公告)日：2019-08-08

申请号：US15888366

申请日：2018-02-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Somnath Ghosh ,  Eswar Ramanathan ,  Qanit Takmeel ,  Ming He ,  Jeric Sarad ,  Ashwini Chandrashekar ,  Colin Bombardier ,  Anbu Selvam KM Mahalingam ,  Keith P. Donegan ,  Prakash Periasamy

IPC: H01L23/544 ,  H01L21/68 ,  G01B11/27 ,  G01N21/552

Abstract: Embodiments of the disclosure provide a substrate structure for an integrated circuit (IC) structure, including: a first dielectric layer positioned above a semiconductor substrate; a first plurality of trenches extending at least partially into the first dielectric layer from an upper surface of the first dielectric layer; and a first metal formed within the first plurality of trenches, wherein a spatial arrangement of the first plurality of trenches causes coupling of surface plasmons in the first metal to at least one wavelength of an incident light.

公开(公告)号：US10818494B2

公开(公告)日：2020-10-27

申请号：US16125066

申请日：2018-09-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hsueh-Chung Chen ,  Ravi P. Srivastava ,  Somnath Ghosh ,  Nicholas V. Licausi ,  Terry A. Spooner ,  Sean Reidy

IPC: B32B3/00 ,  H01L21/033

Abstract: The present disclosure relates to a structure which includes a first metal layer patterned as a mandrel, a dielectric spacer on the first metal layer, and a second metal layer on the dielectric spacer.

公开(公告)号：US10083958B2

公开(公告)日：2018-09-25

申请号：US15292488

申请日：2016-10-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sukeshwar Kannan ,  Somnath Ghosh ,  Daniel Smith ,  Luke England

IPC: H01L27/06 ,  H01L23/66 ,  H01L49/02 ,  H01L23/522

CPC classification number: H01L27/0682 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/53295 ,  H01L23/66 ,  H01L28/20 ,  H01L28/55 ,  H01L28/60 ,  H01L2223/6672

Abstract: Device structures for a metal-insulator-metal (MIM) capacitor, as well as methods of fabricating a device structure for a MIM capacitor. An active device level is formed on a substrate, a local interconnect level is formed on the active device level, and a metal-insulator-metal capacitor is formed in a via opening with a sidewall extending through the local interconnect level and the active device level to a given depth in the substrate. The metal-insulator-metal capacitor includes a first plate on the sidewall, a second plate, and an interplate dielectric between the first plate and the second plate.

公开(公告)号：US20180108651A1

公开(公告)日：2018-04-19

申请号：US15292488

申请日：2016-10-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sukeshwar Kannan ,  Somnath Ghosh ,  Daniel Smith ,  Luke England

IPC: H01L27/06 ,  H01L49/02 ,  H01L23/66 ,  H01L23/522

CPC classification number: H01L27/0682 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/53295 ,  H01L23/66 ,  H01L28/20 ,  H01L28/55 ,  H01L28/60 ,  H01L2223/6672

Abstract: Device structures for a metal-insulator-metal (MIM) capacitor, as well as methods of fabricating a device structure for a MIM capacitor. An active device level is formed on a substrate, a local interconnect level is formed on the active device level, and a metal-insulator-metal capacitor is formed in a via opening with a sidewall extending through the local interconnect level and the active device level to a given depth in the substrate. The metal-insulator-metal capacitor includes a first plate on the sidewall, a second plate, and an interplate dielectric between the first plate and the second plate.

公开(公告)号：US10510675B2

公开(公告)日：2019-12-17

申请号：US15888366

申请日：2018-02-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Somnath Ghosh ,  Eswar Ramanathan ,  Qanit Takmeel ,  Ming He ,  Jeric Sarad ,  Ashwini Chandrashekar ,  Colin Bombardier ,  Anbu Selvam KM Mahalingam ,  Keith P. Donegan ,  Prakash Periasamy

IPC: H01L21/00 ,  H01L23/544 ,  G01N21/552 ,  G01B11/27 ,  H01L21/68

Abstract: Embodiments of the disclosure provide a substrate structure for an integrated circuit (IC) structure, including: a first dielectric layer positioned above a semiconductor substrate; a first plurality of trenches extending at least partially into the first dielectric layer from an upper surface of the first dielectric layer; and a first metal formed within the first plurality of trenches, wherein a spatial arrangement of the first plurality of trenches causes coupling of surface plasmons in the first metal to at least one wavelength of an incident light.