公开(公告)号：US09543219B2

公开(公告)日：2017-01-10

申请号：US14557819

申请日：2014-12-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shawn A. Adderly ,  Samantha D. DiStefano ,  Mark J. Esposito ,  Jeffrey P. Gambino ,  Prakash Periasamy

IPC: H01L21/66 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L22/10 ,  H01L21/67248 ,  H01L21/768 ,  H01L22/30 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of monitoring a temperature of a plurality of regions in a substrate during a deposition process, the monitoring of the temperature including: forming, in the monitored plurality of regions, a plurality of metal structures each with a different metal pattern density, where each metal pattern density corresponds to a threshold temperature at or above which metal voids and surface roughness are formed in the plurality of metal structures, and detecting metal voids and surface roughness in the plurality of metal structures to determine the temperature of the monitored plurality of regions.

Abstract translation: 一种在沉积过程中监测衬底中的多个区域的温度的方法，所述温度的监测包括：在所监视的多个区域中形成多个金属结构，每个金属结构具有不同的金属图案密度，其中每个 金属图案密度对应于多个金属结构中形成金属空隙和表面粗糙度的阈值温度，并且检测多个金属结构中的金属空隙和表面粗糙度，以确定被监测的多个区域的温度。

公开(公告)号：US20160258998A1

公开(公告)日：2016-09-08

申请号：US14635125

申请日：2015-03-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Fen Chen ,  Cathryn J. Christiansen ,  Deborah M. Massey ,  Prakash Periasamy ,  Michael A. Shinosky

IPC: G01R31/28

CPC classification number: G01R31/2858 ,  G01N1/00 ,  H01L21/00 ,  H01L2221/00

Abstract: A system for electromigration testing is disclosed. The system includes a conductive member, a cap layer of insulative material over at least a portion of a top surface of the conductive member, a cathode conductively connected to a first end of the conductive member; an anode conductively connected to a second end of the conductive member, and a current source conductively connected to the cathode and the anode. A plurality of sensory pins are disposed along a length of the conductive member between the first end and the second end of the conductive member. The sensory pins are conductively connected to a bottom surface of the conductive member. At least one measurement device is conductively connected to at least one sensory pin of the plurality of sensory pins. The at least one measurement device determines a resistance of at least one portion of the conductive member.

Abstract translation: 公开了用于电迁移测试的系统。 该系统包括导电构件，在导电构件的顶表面的至少一部分上的绝缘材料的覆盖层，阴极，导电地连接到导电构件的第一端; 导电性地连接到导电构件的第二端的阳极和与阴极和阳极导通地连接的电流源。 沿着导电构件的长度在导电构件的第一端和第二端之间设置多个感应针。 传感针与导电构件的底面导电连接。 至少一个测量装置导电地连接到多个感觉针的至少一个感觉针。 所述至少一个测量装置确定所述导电构件的至少一部分的电阻。

公开(公告)号：US20190244911A1

公开(公告)日：2019-08-08

申请号：US15888366

申请日：2018-02-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Somnath Ghosh ,  Eswar Ramanathan ,  Qanit Takmeel ,  Ming He ,  Jeric Sarad ,  Ashwini Chandrashekar ,  Colin Bombardier ,  Anbu Selvam KM Mahalingam ,  Keith P. Donegan ,  Prakash Periasamy

IPC: H01L23/544 ,  H01L21/68 ,  G01B11/27 ,  G01N21/552

Abstract: Embodiments of the disclosure provide a substrate structure for an integrated circuit (IC) structure, including: a first dielectric layer positioned above a semiconductor substrate; a first plurality of trenches extending at least partially into the first dielectric layer from an upper surface of the first dielectric layer; and a first metal formed within the first plurality of trenches, wherein a spatial arrangement of the first plurality of trenches causes coupling of surface plasmons in the first metal to at least one wavelength of an incident light.

公开(公告)号：US10078183B2

公开(公告)日：2018-09-18

申请号：US14966781

申请日：2015-12-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shawn A. Adderly ,  Samantha D. DiStefano ,  Jeffrey P. Gambino ,  Prakash Periasamy ,  Donald R. Letourneau

IPC: G02B6/13 ,  G02B6/12 ,  G02B6/30 ,  G02B6/136 ,  G02B6/122

CPC classification number: G02B6/30 ,  G02B6/122 ,  G02B6/13 ,  G02B6/136 ,  G02B6/4243 ,  G02B6/4274

Abstract: The disclosure relates to semiconductor structures and, more particularly, to waveguide structures used in phonotics chip packaging and methods of manufacture. The structure includes: a first die comprising photonics functions including a waveguide structure; a second die bonded to the first die and comprising CMOS logic functions; and an optical fiber optically coupled to the waveguide structure and positioned within a cavity formed in the second die.

公开(公告)号：US09851397B2

公开(公告)日：2017-12-26

申请号：US14635125

申请日：2015-03-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Fen Chen ,  Cathryn J. Christiansen ,  Deborah M. Massey ,  Prakash Periasamy ,  Michael A. Shinosky

IPC: G01R31/00 ,  G01R31/28 ,  H01L21/00 ,  G01N1/00

CPC classification number: G01R31/2858 ,  G01N1/00 ,  H01L21/00 ,  H01L2221/00

Abstract: A system for electromigration testing is disclosed. The system includes a conductive member, a cap layer of insulative material over at least a portion of a top surface of the conductive member, a cathode conductively connected to a first end of the conductive member; an anode conductively connected to a second end of the conductive member, and a current source conductively connected to the cathode and the anode. A plurality of sensory pins are disposed along a length of the conductive member between the first end and the second end of the conductive member. The sensory pins are conductively connected to a bottom surface of the conductive member. At least one measurement device is conductively connected to at least one sensory pin of the plurality of sensory pins. The at least one measurement device determines a resistance of at least one portion of the conductive member.

公开(公告)号：US10510675B2

公开(公告)日：2019-12-17

申请号：US15888366

申请日：2018-02-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Somnath Ghosh ,  Eswar Ramanathan ,  Qanit Takmeel ,  Ming He ,  Jeric Sarad ,  Ashwini Chandrashekar ,  Colin Bombardier ,  Anbu Selvam KM Mahalingam ,  Keith P. Donegan ,  Prakash Periasamy

IPC: H01L21/00 ,  H01L23/544 ,  G01N21/552 ,  G01B11/27 ,  H01L21/68

Abstract: Embodiments of the disclosure provide a substrate structure for an integrated circuit (IC) structure, including: a first dielectric layer positioned above a semiconductor substrate; a first plurality of trenches extending at least partially into the first dielectric layer from an upper surface of the first dielectric layer; and a first metal formed within the first plurality of trenches, wherein a spatial arrangement of the first plurality of trenches causes coupling of surface plasmons in the first metal to at least one wavelength of an incident light.

公开(公告)号：US20170168242A1

公开(公告)日：2017-06-15

申请号：US14966781

申请日：2015-12-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shawn A. Adderly ,  Samantha D. DiStefano ,  Jeffrey P. Gambino ,  Prakash Periasamy ,  Donald R. Letourneau

IPC: G02B6/30 ,  G02B6/122 ,  G02B6/13 ,  G02B6/136

CPC classification number: G02B6/30 ,  G02B6/122 ,  G02B6/13 ,  G02B6/136

Abstract: The disclosure relates to semiconductor structures and, more particularly, to waveguide structures used in phonotics chip packaging and methods of manufacture. The structure includes: a first die comprising photonics functions including a waveguide structure; a second die bonded to the first die and comprising CMOS logic functions; and an optical fiber optically coupled to the waveguide structure and positioned within a cavity formed in the second die.