公开(公告)号：US20170323855A1

公开(公告)日：2017-11-09

申请号：US15594059

申请日：2017-05-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Edward C. Cooney, III ,  Laurie M. Krywanczyk

IPC: H01L23/544

CPC classification number: H01L23/544 ,  H01L21/268 ,  H01L21/31053 ,  H01L21/31056 ,  H01L21/76819 ,  H01L23/585 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/54433 ,  H01L2223/5446 ,  H01L2223/54493

Abstract: Structures that include an identification marking and fabrication methods for such structures. A chip is formed within a usable area of a wafer, and a marking region is formed on the wafer. The marking region is comprised of a conductor used to form a last metal layer of an interconnect structure for the chip. The identification marking is formed in the conductor of the marking region. After the identification marking is formed, a dielectric layer is deposited on the marking region. The dielectric layer on the marking region is planarized.

公开(公告)号：US09728509B1

公开(公告)日：2017-08-08

申请号：US15147525

申请日：2016-05-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Edward C. Cooney, III ,  Laurie M. Krywanczyk

IPC: H01L23/544 ,  H01L23/528 ,  H01L23/58 ,  H01L21/768 ,  H01L21/268 ,  H01L21/3105 ,  H01L21/304 ,  H01L23/532

CPC classification number: H01L23/544 ,  H01L21/268 ,  H01L21/31053 ,  H01L21/31056 ,  H01L21/768 ,  H01L23/585 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/54433 ,  H01L2223/5446 ,  H01L2223/54493

Abstract: Structures that include an identification marking and fabrication methods for such structures. A chip is formed within a usable area of a wafer, and a marking region is formed on the wafer. The marking region is comprised of a conductor used to form a last metal layer of an interconnect structure for the chip. The identification marking is formed in the conductor of the marking region. After the identification marking is formed, a dielectric layer is deposited on the marking region. The dielectric layer on the marking region is planarized.