公开(公告)号：US11912902B2

公开(公告)日：2024-02-27

申请号：US16228780

申请日：2018-12-21

申请人： SOULBRAIN CO., LTD.

发明人： Jae-Wan Park ,  Jung-Hun Lim ,  Jin-Uk Lee

IPC分类号： C09G1/04 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/311 ,  H10B43/27 ,  H10B43/35 ,  H01L21/762

CPC分类号： C09G1/04 ,  H01L21/02458 ,  H01L21/31056 ,  H01L21/31111 ,  H10B43/27 ,  H10B43/35 ,  H01L21/76224

摘要： The present invention relates to a composition for etching, comprising a first inorganic acid, a first additive represented by Chemical Formula 1, and a solvent.
The composition for etching is a high-selectivity composition that can selectively remove a nitride film while minimizing the etch rate of an oxide film, and which does not have problems such as particle generation, which adversely affect the device characteristics.

公开(公告)号：US11791390B2

公开(公告)日：2023-10-17

申请号：US17530275

申请日：2021-11-18

申请人： SK hynix Inc.

发明人： Se-Han Kwon ,  Dong-Soo Kim

IPC分类号： H01L29/49 ,  H01L29/423 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/67 ,  H01L21/28 ,  H01L21/3105 ,  H10B12/00

CPC分类号： H01L29/4236 ,  H01L21/0217 ,  H01L21/28088 ,  H01L21/31056 ,  H01L21/32136 ,  H01L21/67075 ,  H01L29/4238 ,  H01L29/42368 ,  H01L29/4966 ,  H01L29/4991 ,  H10B12/053 ,  H10B12/34

摘要： Disclosed is a semiconductor device for improving a gate induced drain leakage and a method for fabricating the same, and the method may include forming a trench in a substrate, lining a surface of the trench with an initial gate dielectric layer, forming a gate electrode to partially fill the lined trench, forming a sacrificial material spaced apart from a top surface of the gate electrode and to selectively cover a top corner of the lined trench, removing a part of the initial gate dielectric layer of the lined trench which is exposed by the sacrificial material in order to form an air gap, and forming a capping layer to cap a side surface of the air gap, over the gate electrode.

公开(公告)号：US20230261115A1

公开(公告)日：2023-08-17

申请号：US17672636

申请日：2022-02-15

申请人： Tokyo Electron Limited

发明人： Mark I. Gardner ,  H. Jim Fulford

IPC分类号： H01L29/786 ,  H01L21/321 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/027

CPC分类号： H01L29/78642 ,  H01L21/3212 ,  H01L29/66045 ,  H01L21/31056 ,  H01L21/0273 ,  H01L21/823418

摘要： A method for fabricating semiconductor devices, may include forming a dielectric having a central portion with top and bottom surfaces thereof. A first sacrificial material and a second sacrificial material may be formed on the top and bottom surfaces, respectively, of the dielectric. End portions of the dielectric may be replaced with a first source/drain (S/D) metal and a second S/D metal. The central portion of the dielectric may be exposed at least by removing the first sacrificial material and second sacrificial material. Two-dimensional (2D) material may be selectively grown around the central portion of the dielectric

公开(公告)号：US11648557B2

公开(公告)日：2023-05-16

申请号：US16581837

申请日：2019-09-25

申请人： International Business Machines Corporation

发明人： Huan Hu ,  Joshua T. Smith ,  Gustavo A. Stolovitzky ,  Benjamin H. Wunsch

IPC分类号： B01L3/00 ,  H01L21/3105 ,  H01L21/3213 ,  H01L29/06 ,  B82Y5/00 ,  G01N15/02 ,  B82Y15/00 ,  H01L21/306 ,  G01N15/00

CPC分类号： B01L3/502753 ,  B82Y5/00 ,  B82Y15/00 ,  G01N15/0255 ,  H01L21/31055 ,  H01L21/31056 ,  H01L21/3213 ,  H01L29/0676 ,  B01L2200/0652 ,  B01L2200/12 ,  B01L2300/0896 ,  B01L2400/086 ,  G01N2015/0053 ,  G01N2015/0065 ,  G01N2015/0288 ,  H01L21/30604

摘要： Techniques relate to forming a sorting device. A mesh is formed on top of a substrate. Metal assisted chemical etching is performed to remove substrate material of the substrate at locations of the mesh. Pillars are formed in the substrate by removal of the substrate material. The mesh is removed to leave the pillars in a nanopillar array. The pillars in the nanopillar array are designed with a spacing to sort particles of different sizes such that the particles at or above a predetermined dimension are sorted in a first direction and the particles below the predetermined dimension are sorted in a second direction.

公开(公告)号：US20180374921A1

公开(公告)日：2018-12-27

申请号：US16120855

申请日：2018-09-04

申请人： Infineon Technologies AG

发明人： Albert Birner ,  Helmut Brech ,  Simone Lavanga

IPC分类号： H01L29/205 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/304 ,  H01L21/762 ,  H01L29/20 ,  H01L29/10 ,  H01L29/66 ,  H01L29/778

CPC分类号： H01L29/205 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0254 ,  H01L21/304 ,  H01L21/31053 ,  H01L21/31056 ,  H01L21/76229 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7786

摘要： In an embodiment, a semiconductor wafer includes a substrate wafer having a device surface region surrounded by a peripheral region, one or more mesas including a Group III nitride layer arranged on the device surface region, and an oxide layer arranged on the device surface region and on the peripheral region. The oxide layer has an upper surface that is substantially coplanar with an upper surface of the one or more mesas.

公开(公告)号：US10083882B2

公开(公告)日：2018-09-25

申请号：US15608558

申请日：2017-05-30

申请人： International Business Machines Corporation

发明人： Karthik Balakrishnan ,  Pouya Hashemi ,  Sanghoon Lee

IPC分类号： H01L21/76 ,  H01L21/84 ,  H01L21/308 ,  H01L21/02 ,  H01L27/12 ,  H01L21/306 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/04 ,  H01L29/423 ,  H01L29/06 ,  H01L29/20

CPC分类号： H01L21/845 ,  H01L21/02381 ,  H01L21/02428 ,  H01L21/02433 ,  H01L21/02538 ,  H01L21/02639 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/3081 ,  H01L21/31056 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/6681 ,  H01L29/7853 ,  H01L29/78654 ,  H01L29/78681 ,  H01L29/78696

摘要： A method for forming a nanowire device comprises depositing a hard mask on portions of a silicon substrate having a orientation wherein the hard mask is oriented in the direction, etching the silicon substrate to form a mandrel having (111) faceted sidewalls; forming a layer of insulator material on the substrate; forming a sacrificial stack comprising alternating layers of sacrificial material and dielectric material disposed on the layer of insulator material and adjacent to the mandrel; patterning and etching the sacrificial stack to form a modified sacrificial stack adjacent to the mandrel and extending from the mandrel; removing the sacrificial material from the modified sacrificial stack to form growth channels; epitaxially forming semiconductor in the growth channels; and etching the semiconductor to align with the end of the growth channels and form a semiconductor stack comprising alternating layers of dielectric material and semiconductor material.

公开(公告)号：US09984916B2

公开(公告)日：2018-05-29

申请号：US15400643

申请日：2017-01-06

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Michael Rizzolo ,  Jay W. Strane

IPC分类号： H01L21/8234 ,  H01L21/762 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/311

CPC分类号： H01L21/76232 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/31051 ,  H01L21/31055 ,  H01L21/31056 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76229 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/66795

摘要： A method for providing a uniform recess depth between different fin gap sizes includes depositing a dielectric material between fins on a substrate. Etch lag is tuned for etching the dielectric material between narrow gaps faster than the dielectric material between wider gaps such that the dielectric material in the narrow gaps reaches a target depth. An etch block is formed in the narrow gaps. The wider gaps are etched to the target depth. The etch block is removed.

公开(公告)号：US09972498B2

公开(公告)日：2018-05-15

申请号：US15081932

申请日：2016-03-27

申请人： UNITED MICROELECTRONICS CORP.

发明人： Fu-Shou Tsai ,  Yu-Ting Li ,  Chih-Hsun Lin ,  Li-Chieh Hsu ,  Yi-Liang Liu ,  Po-Cheng Huang ,  Kun-Ju Li ,  Wen-Chin Lin

IPC分类号： B23P15/00 ,  C03C25/00 ,  C23F1/00 ,  B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  H01L21/28 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3105

CPC分类号： H01L21/28247 ,  H01L21/0223 ,  H01L21/02247 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/31053 ,  H01L21/31056 ,  H01L29/66545

摘要： A method of fabricating a gate cap layer includes providing a substrate with an interlayer dielectric disposed thereon, wherein a recess is disposed in the interlayer dielectric and a metal gate fills in a lower portion of the recess. Later, a cap material layer is formed to cover the interlayer dielectric and fill in an upper portion of the recess. After that, a first sacrifice layer and a second sacrifice layer are formed in sequence to cover the cap material layer. The first sacrifice layer has a composition different from a composition of the cap material layer. The second sacrifice layer has a composition the same as the composition of the cap material layer. Next, a chemical mechanical polishing process is preformed to remove the second sacrifice layer, the first sacrifice layer and the cap material layer above a top surface of the interlayer dielectric.

公开(公告)号：US09947535B2

公开(公告)日：2018-04-17

申请号：US15368966

申请日：2016-12-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tsung-Min Huang ,  Chung-Ju Lee ,  Yung-Hsu Wu

IPC分类号： H01L21/44 ,  H01L21/033 ,  H01L21/768 ,  H01L21/311 ,  H01L21/32 ,  H01L21/321 ,  H01L21/3105 ,  H01L23/532

CPC分类号： H01L21/0338 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31056 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method includes forming a mandrel layer over a target layer, and etching the mandrel layer to form mandrels. The mandrels have top widths greater than respective bottom widths, and the mandrels define a first opening in the mandrel layer. The first opening has an I-shape and includes two parallel portions and a connecting portion interconnecting the two parallel portions. Spacers are formed on sidewalls of the first opening. The spacers fill the connecting portion, wherein a center portion of each of the two parallel portions is unfilled by the spacers. Portions of the first opening that are unfilled by the spacers are extended into the target layer.

公开(公告)号：US09917057B2

公开(公告)日：2018-03-13

申请号：US15361757

申请日：2016-11-28

申请人： International Business Machines Corporation

发明人： Josephine B. Chang ,  Szu-Lin Cheng ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC分类号： H01L23/532 ,  H01L21/311 ,  H01L21/02 ,  H01L21/768 ,  H01L21/324 ,  H01L23/528 ,  H01L21/3105

CPC分类号： H01L23/53228 ,  H01L21/02134 ,  H01L21/02282 ,  H01L21/02351 ,  H01L21/31056 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/324 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one aspect, a method of forming a wiring layer on a wafer is provided which includes: depositing a HSQ layer onto the wafer; cross-linking a first portion(s) of the HSQ layer using e-beam lithography; depositing a hardmask material onto the HSQ layer; patterning the hardmask using optical lithography, wherein the patterned hardmask covers a second portion(s) of the HSQ layer; patterning the HSQ layer using the patterned hardmask in a manner such that i) the first portion(s) of the HSQ layer remain and ii) the second portion(s) of the HSQ layer covered by the patterned hardmask remain, wherein by way of the patterning step trenches are formed in the HSQ layer; and filling the trenches with a conductive material to form the wiring layer on the wafer.