公开(公告)号：US09761329B2

公开(公告)日：2017-09-12

申请号：US14918149

申请日：2015-10-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Aravindan J. Busi ,  Deepak I. Hanagandi ,  Krishnendu Mondal ,  Michael R. Ouellette

IPC: G11C29/38 ,  G11C29/18 ,  G11C29/44 ,  G11C29/04

CPC classification number: G11C29/38 ,  G11C29/18 ,  G11C29/44 ,  G11C2029/0401

Abstract: An integrated circuit chip with a built-in self-test (BIST) circuit having a BIST engine, which is electrically connected to multiple memories, which tests those multiple memories in parallel, and which incorporates an address generator. Prior to testing, the address generator generates a pair of tables. The tables include a first table, which indicates the highest decode numbers per specific bank numbers in all of the multiple memories, and a second table, which indicates the highest bank numbers per specific decode numbers in all of the multiple memories. During testing, the address generator sequentially and dynamically generates the specific test addresses to be swept and does so such that all of the specific test addresses are within a composite address space that is defined by one of the tables and by the highest maximum word line number in any of the memories. Also disclosed is an associated BIST method.

公开(公告)号：US10014074B2

公开(公告)日：2018-07-03

申请号：US15136404

申请日：2016-04-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Krishnendu Mondal ,  Deepak I. Hanagandi ,  Michael R. Ouellette ,  Valerie H. Chickanosky

IPC: G11C29/00 ,  G11C29/44 ,  G11C29/38

CPC classification number: G11C29/44 ,  G11C29/38 ,  G11C29/4401

Abstract: A built-in self-test (BIST) system comprising repair logic structured to share state logic of failed memories across local registers located in a shared registry which services multiple memories, wherein each of the local registers is associated with a different memory.

公开(公告)号：US20170110205A1

公开(公告)日：2017-04-20

申请号：US14918149

申请日：2015-10-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Aravindan J. Busi ,  Deepak I. Hanagandi ,  Krishnendu Mondal ,  Michael R. Ouellette

IPC: G11C29/38 ,  G11C29/18 ,  G11C29/44

CPC classification number: G11C29/38 ,  G11C29/18 ,  G11C29/44 ,  G11C2029/0401

Abstract: Disclosed is an integrated circuit chip with a built-in self-test (BIST) circuit having a BIST engine, which is electrically connected to multiple memories, which tests those multiple memories in parallel, and which incorporates an address generator. Prior to testing, the address generator generates a pair of tables. The tables include a first table, which indicates the highest decode numbers per specific bank numbers in all of the multiple memories, and a second table, which indicates the highest bank numbers per specific decode numbers in all of the multiple memories. During testing, the address generator sequentially and dynamically generates the specific test addresses to be swept and does so such that all of the specific test addresses are within a composite address space that is defined by one of the tables and by the highest maximum word line number in any of the memories. Also disclosed is an associated BIST method.

公开(公告)号：US20170229191A1

公开(公告)日：2017-08-10

申请号：US15019590

申请日：2016-02-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michael R. Ouellette ,  Deepak I. Hanagandi ,  Aravindan J. Busi ,  Kiran K. Narayan ,  Michael A. Ziegerhofer

IPC: G11C29/44 ,  G11C29/36

CPC classification number: G11C29/44 ,  G11C29/10 ,  G11C29/36 ,  G11C29/4401 ,  G11C2029/3602 ,  G11C2029/4402

Abstract: Approaches for a memory built-in self-test (MBIST) are provided. The MBIST circuit includes a fail status register which receives a new fail signal value in response to a detection of a unique fail in a pattern, and a pattern mask register which stores at an end of the pattern a different value of the new fail signal value representative of the unique fail.

公开(公告)号：US09286181B2

公开(公告)日：2016-03-15

申请号：US13955401

申请日：2013-07-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Craig M. Monroe ,  Michael R. Ouellette ,  Douglas E. Sprague ,  Michael A. Ziegerhofer

IPC: G01R31/28 ,  G06F11/27 ,  G11C29/44 ,  G11C29/56 ,  G11C29/12

CPC classification number: G06F11/27 ,  G11C29/44 ,  G11C29/56008 ,  G11C2029/1208 ,  G11C2029/4402 ,  G11C2029/5606

Abstract: A method to produce a description file of Joint Test Action Group (JTAG) capture-shift test data registers to be used to interpret a test result of a memory included in an integrated circuit structure that is configured for testing integrated circuit memory. A computer extracts, from a first data file, the names a memory built in self test instance, a memory built in self test port name, and a name of a first memory. The first data file controls the hierarchical and architectural arrangement of components of an integrated circuit. The first data file describes a hierarchical order of an architectural arrangement of the components, electrical pathways, and connections between the components and the electrical pathways of an integrated circuit design. The computer adds the extracted names into the description file such that the description file is configured to interpret a test result of a memory.

Abstract translation: 一种用于产生联合测试动作组（JTAG）捕捉移位测试数据寄存器的描述文件的方法，用于解释包含在被配置用于测试集成电路存储器的集成电路结构中的存储器的测试结果。 计算机从第一数据文件中提取内置于自检实例中的内存的名称，内置于自测试端口名称的内存和第一存储器的名称。 第一个数据文件控制集成电路组件的分层结构和架构布置。 第一数据文件描述了组件的结构布置，电路径以及组件与集成电路设计的电路之间的连接的分级顺序。 计算机将提取的名称添加到描述文件中，使得描述文件被配置为解释存储器的测试结果。