公开(公告)号：US09368590B2

公开(公告)日：2016-06-14

申请号：US14073581

申请日：2013-11-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Susan S. Fan ,  Balasubramanian S. Haran ,  David V. Horak ,  Charles W. Koburger

IPC: H01L21/28 ,  H01L21/70 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786 ,  H01L27/12 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/42384 ,  H01L21/76834 ,  H01L21/76897 ,  H01L27/088 ,  H01L27/1207 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/78651 ,  H01L29/78654

Abstract: A method is provided for fabricating an integrated circuit that includes multiple transistors. A replacement gate stack is formed on a semiconductor layer, a gate spacer is formed, and a dielectric layer is formed. The dummy gate stack is removed to form a cavity. A gate dielectric and a work function metal layer are formed in the cavity. The cavity is filled with a gate conductor. One and only one of the gate conductor and the work function metal layer are selectively recessed. An oxide film is formed in the recess such that its upper surface is co-planar with the upper surface of the dielectric layer. The oxide film is used to selectively grow an oxide cap. An interlayer dielectric is formed and etched to form a cavity for a source/drain contact. A source/drain contact is formed in the contact cavity, with a portion of the source/drain contact being located directly on the oxide cap.

Abstract translation: 提供了一种用于制造包括多个晶体管的集成电路的方法。 在半导体层上形成替代栅极叠层，形成栅极间隔物，形成电介质层。 去除虚拟栅极堆叠以形成空腔。 在空腔中形成栅极电介质和功函数金属层。 空腔填充有栅极导体。 门导体和功函数金属层中的仅一个选择性地凹入。 在凹部中形成氧化膜，使得其上表面与电介质层的上表面共面。 氧化膜用于选择性地生长氧化物盖。 形成并蚀刻层间电介质以形成用于源/漏接触的空腔。 源极/漏极接触形成在接触腔中，源极/漏极触点的一部分直接位于氧化物盖上。