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    Silicon-on-insulator transistor with self-aligned borderless source/drain contacts
    1.
    发明授权
    Silicon-on-insulator transistor with self-aligned borderless source/drain contacts 有权
    具有自对准无边界源极/漏极触点的绝缘体上硅晶体管

    公开(公告)号：US09368590B2

    公开(公告)日：2016-06-14

    申请号：US14073581

    申请日：2013-11-06

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Susan S. Fan ,  Balasubramanian S. Haran ,  David V. Horak ,  Charles W. Koburger

    IPC: H01L21/28 ,  H01L21/70 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786 ,  H01L27/12 ,  H01L27/088 ,  H01L29/78

    CPC classification number: H01L29/42384 ,  H01L21/76834 ,  H01L21/76897 ,  H01L27/088 ,  H01L27/1207 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/78651 ,  H01L29/78654

    Abstract: A method is provided for fabricating an integrated circuit that includes multiple transistors. A replacement gate stack is formed on a semiconductor layer, a gate spacer is formed, and a dielectric layer is formed. The dummy gate stack is removed to form a cavity. A gate dielectric and a work function metal layer are formed in the cavity. The cavity is filled with a gate conductor. One and only one of the gate conductor and the work function metal layer are selectively recessed. An oxide film is formed in the recess such that its upper surface is co-planar with the upper surface of the dielectric layer. The oxide film is used to selectively grow an oxide cap. An interlayer dielectric is formed and etched to form a cavity for a source/drain contact. A source/drain contact is formed in the contact cavity, with a portion of the source/drain contact being located directly on the oxide cap.

    Abstract translation: 提供了一种用于制造包括多个晶体管的集成电路的方法。 在半导体层上形成替代栅极叠层，形成栅极间隔物，形成电介质层。 去除虚拟栅极堆叠以形成空腔。 在空腔中形成栅极电介质和功函数金属层。 空腔填充有栅极导体。 门导体和功函数金属层中的仅一个选择性地凹入。 在凹部中形成氧化膜，使得其上表面与电介质层的上表面共面。 氧化膜用于选择性地生长氧化物盖。 形成并蚀刻层间电介质以形成用于源/漏接触的空腔。 源极/漏极接触形成在接触腔中，源极/漏极触点的一部分直接位于氧化物盖上。

    Dual damascene dual alignment interconnect scheme
    3.
    发明授权
    Dual damascene dual alignment interconnect scheme 有权
    双镶嵌双对准互连方案

    公开(公告)号：US09269621B2

    公开(公告)日：2016-02-23

    申请号：US14449314

    申请日：2014-08-01

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

    IPC: H01L21/311 ,  H01L21/44 ,  H01L21/768 ,  H01L23/522

    CPC classification number: H01L21/76897 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76883 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A stack of a first metal line and a first dielectric cap material portion is formed within a line trench of first dielectric material layer. A second dielectric material layer is formed thereafter. A line trench extending between the top surface and the bottom surface of the second dielectric material layer is patterned. A photoresist layer is applied over the second dielectric material layer and patterned with a via pattern. An underlying portion of the first dielectric cap material is removed by an etch selective to the dielectric materials of the first and second dielectric material layer to form a via cavity that is laterally confined along the widthwise direction of the line trench and along the widthwise direction of the first metal line. A dual damascene line and via structure is formed, which includes a via structure that is laterally confined along two independent horizontal directions.

    Abstract translation: 在第一介电材料层的线沟槽内形成第一金属线和第一介电帽材料部分的堆叠。 之后形成第二电介质材料层。 在第二介电材料层的顶表面和底表面之间延伸的线沟槽被图案化。 将光致抗蚀剂层施加在第二介电材料层上并用通孔图案构图。 通过对第一和第二介电材料层的介电材料的选择性蚀刻来去除第一电介质盖材料的下部，以形成沿着线沟槽的宽度方向横向限制并沿着宽度方向的 第一条金属线。 形成双镶嵌线和通孔结构，其包括沿着两个独立的水平方向横向限制的通孔结构。

    Integrated circuits having gate cap protection and methods of forming the same
    4.
    发明授权
    Integrated circuits having gate cap protection and methods of forming the same 有权
    具有栅极盖保护的集成电路及其形成方法

    公开(公告)号：US09269611B2

    公开(公告)日：2016-02-23

    申请号：US14159944

    申请日：2014-01-21

    Applicant: GLOBALFOUNDRIES, Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Daniel Thanh Khae Pham ,  Xiuyu Cai ,  Bala Subramanian Pranatharthi Haran ,  Charan Veera Venkata Satya Surisetty ,  Jin Wook Lee ,  Shom Ponoth ,  David V. Horak

    IPC: H01L29/78 ,  H01L21/768

    CPC classification number: H01L21/76816 ,  H01L21/28247 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Integrated circuits and methods of forming integrated circuits are provided. An integrated circuit includes a gate electrode structure overlying a base substrate. The gate electrode structure includes a gate electrode, with a cap disposed over the gate electrode and sidewall spacers disposed adjacent to sidewalls of the gate electrode structure. A source and drain region are formed in the base substrate aligned with the gate electrode structure. A first dielectric layer is disposed adjacent to the sidewall spacers. The sidewall spacers and the cap have recessed surfaces below a top surface of the first dielectric layer, and a protecting layer is disposed over the recessed surfaces. A second dielectric layer is disposed over the first dielectric layer and the protecting layer. Electrical interconnects are disposed through the first dielectric layer and the second dielectric layer, and the electrical interconnects are in electrical communication with the respective source and drain regions.

    Abstract translation: 提供了形成集成电路的集成电路和方法。 集成电路包括覆盖基底的栅电极结构。 栅极电极结构包括栅电极，栅极设置在栅电极上，侧壁间隔件邻近栅电极结构的侧壁设置。 源极和漏极区域形成在与栅电极结构对准的基底衬底中。 第一电介质层设置成与侧壁间隔物相邻。 侧壁间隔件和盖在第一电介质层的顶表面下方具有凹陷表面，并且保护层设置在凹入表面之上。 第二电介质层设置在第一电介质层和保护层之上。 电互连通过第一介电层和第二介电层设置，并且电互连与相应的源区和漏区电连通。

    SUB-LITHOGRAPHIC SEMICONDUCTOR STRUCTURES WITH NON-CONSTANT PITCH
    5.
    发明申请
    SUB-LITHOGRAPHIC SEMICONDUCTOR STRUCTURES WITH NON-CONSTANT PITCH 有权
    具有非常数PITCH的次平面半导体结构

    公开(公告)号：US20150380262A1

    公开(公告)日：2015-12-31

    申请号：US14843085

    申请日：2015-09-02

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Marc A. Bergendahl ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

    IPC: H01L21/308 ,  H01L21/3065

    CPC classification number: H01L21/3088 ,  H01L21/2815 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/3086

    Abstract: Fin structures and methods of manufacturing fin structures using a dual-material sidewall image transfer mask to enable patterning of sub-lithographic features is disclosed. The method of forming a plurality of fins includes forming a first set of fins having a first pitch. The method further includes forming an adjacent fin to the first set of fins. The adjacent fin and a nearest fin of the first set of fins have a second pitch larger than the first pitch. The first set of fins and the adjacent fin are sub-lithographic features formed using a sidewall image transfer process.

    Abstract translation: 公开了使用双材料侧壁图像转印掩模制造翅片结构以实现亚光刻特征图案化的翅片结构和方法。 形成多个翅片的方法包括形成具有第一间距的第一组翅片。 该方法还包括形成与第一组翅片相邻的翅片。 相邻翅片和第一组翅片的最近的翅片具有比第一节距大的第二节距。 第一组翅片和相邻翅片是使用侧壁图像转移过程形成的亚光刻特征。

    Bi-layer gate cap for self-aligned contact formation
    6.
    发明授权
    Bi-layer gate cap for self-aligned contact formation 有权
    用于自对准接触形成的双层栅极盖

    公开(公告)号：US09064801B1

    公开(公告)日：2015-06-23

    申请号：US14161721

    申请日：2014-01-23

    Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc. ,  Samsung Electronics Co., Ltd.

    Inventor： David V. Horak ,  Jin Wook Lee ,  Daniel Pham ,  Shom S. Ponoth ,  Balasubramanian Pranatharthiharan

    IPC: H01L21/336 ,  H01L21/28 ,  H01L29/51 ,  H01L21/283

    CPC classification number: H01L21/283 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628

    Abstract: A method of forming a semiconductor structure includes forming a metal gate above a semiconductor substrate and gate spacers adjacent to the metal gate surrounded by an interlevel dielectric (ILD) layer. The gate spacers and the metal gate are recessed until a height of the metal gate is less than a height of the gate spacers. An etch stop liner is deposited above the gate spacers and the metal gate. A gate cap is deposited above the etch stop liner to form a bi-layer gate cap. A contact hole is formed in the ILD layer adjacent to the metal gate, the etch stop liner in the bi-layer gate cap prevents damage of the gate spacers during formation of the contact hole. A conductive material is deposited in the contact hole to form a contact to a source-drain region in the semiconductor substrate.

    Abstract translation: 形成半导体结构的方法包括在半导体衬底之上形成金属栅极和邻近由层间电介质（ILD）层围绕的金属栅极的栅极间隔。 栅极间隔物和金属栅极凹入直到金属栅极的高度小于栅极间隔物的高度。 蚀刻停止衬垫沉积在栅极间隔物和金属栅极上方。 栅极盖沉积在蚀刻停止衬垫上方以形成双层栅极盖。 在与金属栅极相邻的ILD层中形成接触孔，双层栅极帽中的蚀刻停止衬垫防止在形成接触孔期间损坏栅极间隔物。 导电材料沉积在接触孔中以与半导体衬底中的源极 - 漏极区形成接触。

    Dual hard mask lithography process
    9.
    发明授权
    Dual hard mask lithography process 有权
    双硬掩模光刻工艺

    公开(公告)号：US09373580B2

    公开(公告)日：2016-06-21

    申请号：US14140060

    申请日：2013-12-24

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： John C. Arnold ,  Sean D. Burns ,  Steven J. Holmes ,  David V. Horak ,  Muthumanickam Sankarapandian ,  Yunpeng Yin

    IPC: H01L21/00 ,  H01L23/522 ,  G03F7/00 ,  G03F7/09 ,  H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L21/308

    CPC classification number: H01L23/5226 ,  G03F7/0035 ,  G03F7/091 ,  G03F7/094 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816 ,  H01L2924/0002 ,  Y10T428/24355 ,  H01L2924/00

    Abstract: A first metallic hard mask layer over an interconnect-level dielectric layer is patterned with a line pattern. At least one dielectric material layer, a second metallic hard mask layer, a first organic planarization layer (OPL), and a first photoresist are applied above the first metallic hard mask layer. A first via pattern is transferred from the first photoresist layer into the second metallic hard mask layer. A second OPL and a second photoresist are applied and patterned with a second via pattern, which is transferred into the second metallic hard mask layer. A first composite pattern of the first and second via patterns is transferred into the at least one dielectric material layer. A second composite pattern that limits the first composite pattern with the areas of the openings in the first metallic hard mask layer is transferred into the interconnect-level dielectric layer.

    Abstract translation: 在互连级介质层上的第一金属硬掩模层用线图案图案化。 在第一金属硬掩模层上方施加至少一个介电材料层，第二金属硬掩模层，第一有机平坦化层（OPL）和第一光致抗蚀剂。 第一通孔图案从第一光致抗蚀剂层转移到第二金属硬掩模层中。 第二OPL和第二光致抗蚀剂被施加和图案化，第二通孔图案被转移到第二金属硬掩模层中。 第一和第二通孔图案的第一复合图案被转移到至少一个介电材料层中。 将第一复合图案与第一金属硬掩模层中的开口的面积限制的第二复合图案被转移到互连级介质层中。

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