公开(公告)号：US20160225919A1

公开(公告)日：2016-08-04

申请号：US14612639

申请日：2015-02-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Fen Chen ,  Carole D. Graas ,  Terence L. Kane ,  Michael A. Shinosky

IPC: H01L29/94 ,  H01L29/32

CPC classification number: H01L29/945 ,  H01L29/495 ,  H01L29/518 ,  H01L47/005

Abstract: Device structures that exhibit negative resistance characteristics and fabrication methods for such device structures. A signal is applied to a metal layer of a metal-insulator-semiconductor capacitor to cause a breakdown of an insulator layer of the metal-insulator-semiconductor capacitor at a location. The breakdown at the location of the insulator layer causes the metal-insulator-semiconductor capacitor to exhibit negative resistance. The metal layer may be comprised of a polycrystalline metal. A grain of the polycrystalline metal may penetrate through the insulator layer and into a portion of a substrate at the location of the breakdown.

Abstract translation: 显示负电阻特性的器件结构和这种器件结构的制造方法。 将信号施加到金属 - 绝缘体 - 半导体电容器的金属层，以使金属 - 绝缘体 - 半导体电容器的绝缘体层在一处发生击穿。 在绝缘体层的位置处的击穿导致金属 - 绝缘体 - 半导体电容器呈现负电阻。 金属层可以由多晶金属构成。 多晶金属的晶粒可以在击穿位置处穿过绝缘体层并进入衬底的一部分。

公开(公告)号：US20180138209A1

公开(公告)日：2018-05-17

申请号：US15351678

申请日：2016-11-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wen Liu ,  Criag M. Bocash ,  Carole D. Graas ,  Fen Chen

IPC: H01L27/12 ,  H01L23/373 ,  H01L21/3115 ,  H01L21/762

CPC classification number: H01L27/1211 ,  H01L21/02002 ,  H01L21/76251 ,  H01L21/76256 ,  H01L27/1203

Abstract: An SOI substrate includes a metallic doped isolation (i.e., buried oxide) layer. Doping of the isolation layer increases its thermal conductivity, which improves heat conduction and decreases the susceptibility of devices formed on the substrate to temperature-induced deterioration and/or failure over time. The amount as well as the configuration of the doping can be tailored to specific circuit architectures.

公开(公告)号：US10388567B2

公开(公告)日：2019-08-20

申请号：US15724493

申请日：2017-10-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Fen Chen ,  Mukta G. Farooq ,  Carole D. Graas ,  Xiao Hu Liu

IPC: H01L21/768 ,  H01L23/48

Abstract: Stress generation free thru-silicon-via structures with improved performance and reliability and methods of manufacture are provided. The method includes forming a first conductive diffusion barrier liner on an insulator layer within a thru-silicon-via of a wafer material. The method further includes forming a stress absorption layer on the first conductive diffusion barrier. The method further includes forming a second conductive diffusion barrier on the stress absorption layer. The method further includes forming a copper plate on the second conductive diffusion barrier.