-
1.
公开(公告)号:US20190237358A1
公开(公告)日:2019-08-01
申请号:US16378114
申请日:2019-04-08
IPC分类号: H01L21/762 , H01L27/146 , H01L27/12
CPC分类号: H01L21/76256 , H01L21/7624 , H01L21/76251 , H01L24/80 , H01L27/1203 , H01L27/14687 , H01L31/1892 , H01L2221/68363 , H01L2224/80896
摘要: A method for fabricating silicon-on-insulator (SOI) semiconductor devices, wherein the piezoresistive pattern is defined within a blanket doped layer after fusion bonding. This new method of fabricating SOI semiconductor devices is more suitable for simpler large scale fabrication as it provides the flexibility to select the device pattern/type at the latest stages of fabrication.
-
公开(公告)号:US20180294183A1
公开(公告)日:2018-10-11
申请号:US15574009
申请日:2016-05-18
发明人: Gang Wang , Shawn George Thomas
IPC分类号: H01L21/762 , H01L21/02 , H01L21/3065
CPC分类号: H01L21/76256 , H01L21/0242 , H01L21/0245 , H01L21/02488 , H01L21/02499 , H01L21/02502 , H01L21/02532 , H01L21/0262 , H01L21/02658 , H01L21/02694 , H01L21/3065 , H01L21/76251
摘要: The disclosed method is suitable for producing a SiGe-on-insulator structure. According to some embodiments of the method, a layer comprising SiGe is deposited on silicon-on-insulator substrate comprising an ultra-thin silicon top layer. In some embodiments, the layer comprising SiGe is deposited by epitaxial deposition. In some embodiments, the SiGe epitaxial layer is high quality since it is produced by engineering the strain relaxation at the Si/buried oxide interface. In some embodiments, the method accomplishes elastic strain relaxation of SiGe grown on a few monolayer thick Si layer that is weakly bonded to the underline oxide.
-
3.
公开(公告)号:US20180277423A1
公开(公告)日:2018-09-27
申请号:US15537734
申请日:2015-12-18
IPC分类号: H01L21/762 , H01L21/66
CPC分类号: H01L21/76256 , H01L21/3065 , H01L21/67115 , H01L21/76254 , H01L22/12 , H01L22/20 , H01L22/26
摘要: Systems and methods for processing semiconductor structures are provided. The methods generally include determining a desired removal map profile for a device layer of a semiconductor structure, determining a set of process parameters for use in an epitaxial smoothing process based on the desired removal map profile, and selectively removing material from the device layer by performing an epitaxial smoothing process on an outer surface of the device layer.
-
公开(公告)号:US20180254197A1
公开(公告)日:2018-09-06
申请号:US15754123
申请日:2016-08-31
发明人: Kwang Hong Lee , Eng Kian Kenneth Lee , Chuan Seng Tan , Eugene A. Fitzgerald , Viet Cuong Nguyen
IPC分类号: H01L21/56 , H01L21/8238 , H01L21/02 , H01L21/762 , H01L21/285
CPC分类号: H01L21/56 , H01L21/02002 , H01L21/28575 , H01L21/76256 , H01L21/8238 , H01L21/8258 , H01L23/3185 , H01L29/00
摘要: A method of encapsulating a substrate is disclosed, in which the substrate has at least the following layers: a CMOS device layer, a layer of first semiconductor material different to silicon, and a layer of second semiconductor material, the layer of first semiconductor material arranged intermediate the CMOS device layer and the layer of second semiconductor material. The method comprises: (i) circumferentially removing a portion of the substrate at the edges; and (ii) depositing a dielectric material on the substrate to replace the portion removed at step (i) for encapsulating at least the CMOS device layer and the layer of first semiconductor material. A related substrate is also disclosed.
-
公开(公告)号:US20180138209A1
公开(公告)日:2018-05-17
申请号:US15351678
申请日:2016-11-15
申请人: GLOBALFOUNDRIES INC.
发明人: Wen Liu , Criag M. Bocash , Carole D. Graas , Fen Chen
IPC分类号: H01L27/12 , H01L23/373 , H01L21/3115 , H01L21/762
CPC分类号: H01L27/1211 , H01L21/02002 , H01L21/76251 , H01L21/76256 , H01L27/1203
摘要: An SOI substrate includes a metallic doped isolation (i.e., buried oxide) layer. Doping of the isolation layer increases its thermal conductivity, which improves heat conduction and decreases the susceptibility of devices formed on the substrate to temperature-induced deterioration and/or failure over time. The amount as well as the configuration of the doping can be tailored to specific circuit architectures.
-
6.
公开(公告)号:US20170330792A1
公开(公告)日:2017-11-16
申请号:US15663078
申请日:2017-07-28
IPC分类号: H01L21/762 , H01L27/146 , H01L27/12 , H01L31/18 , H01L23/00
CPC分类号: H01L21/76256 , H01L21/7624 , H01L21/76251 , H01L24/80 , H01L27/1203 , H01L27/14687 , H01L31/1892 , H01L2221/68363 , H01L2224/80896
摘要: A method for fabricating silicon-on-insulator (SOI) semiconductor devices, wherein the piezoresistive pattern is defined within a blanket doped layer after fusion bonding. This new method of fabricating SOI semiconductor devices is more suitable for simpler large scale fabrication as it provides the flexibility to select the device pattern/type at the latest stages of fabrication.
-
公开(公告)号:US20170316929A1
公开(公告)日:2017-11-02
申请号:US15650504
申请日:2017-07-14
发明人: Helmut Oefner , Nico Caspary , Mohammad Momeni , Reinhard Ploss , Francisco Javier Santos Rodriguez , Hans-Joachim Schulze
IPC分类号: H01L21/02 , H01L21/268 , H01L21/324 , H01L29/66 , H01L21/18 , H01L21/28 , H01L21/322 , H01L21/225
CPC分类号: H01L29/7393 , H01L21/02002 , H01L21/02005 , H01L21/02008 , H01L21/0201 , H01L21/02016 , H01L21/187 , H01L21/2257 , H01L21/268 , H01L21/28238 , H01L21/3221 , H01L21/3225 , H01L21/324 , H01L21/3242 , H01L21/76256 , H01L29/1095 , H01L29/32 , H01L29/66325 , H01L29/66348 , H01L29/66734 , H01L29/7395 , H01L29/7397 , H01L29/7813
摘要: A method for manufacturing a substrate wafer 100 includes providing a device wafer (110) having a first side (111) and a second side (112); subjecting the device wafer (110) to a first high temperature process for reducing the oxygen content of the device wafer (110) at least in a region (112a) at the second side (112); bonding the second side (112) of the device wafer (110) to a first side (121) of a carrier wafer (120) to form a substrate wafer (100); processing the first side (101) of the substrate wafer (100) to reduce the thickness of the device wafer (110); subjecting the substrate wafer (100) to a second high temperature process for reducing the oxygen content at least of the device wafer (110); and at least partially integrating at least one semiconductor component (140) into the device wafer (110) after the second high temperature process.
-
公开(公告)号:US09786613B2
公开(公告)日:2017-10-10
申请号:US14454204
申请日:2014-08-07
发明人: Michael A. Stuber
IPC分类号: H01L23/48 , H01L21/768 , H01L23/60 , H01L21/84 , H01L23/552 , H01L21/683
CPC分类号: H01L23/60 , H01L21/6835 , H01L21/76256 , H01L21/76838 , H01L21/78 , H01L21/84 , H01L23/552 , H01L23/64 , H01L23/66 , H01L25/16 , H01L2221/68327 , H01L2221/6834 , H01L2223/6616 , H01L2223/6672 , H01L2924/0002 , H01L2924/1306 , H01L2924/14 , H01L2924/1421 , H01L2924/1461 , H01L2924/00
摘要: Various methods and devices that involve EMI shields for radio frequency layer transferred devices are disclosed. One method comprises forming a radio frequency field effect transistor in an active layer of a semiconductor on insulator wafer. The semiconductor on insulator wafer has a buried insulator side and an active layer side. The method further comprises bonding a second wafer to the active layer side of the semiconductor on insulator wafer. The method further comprises forming a shield layer for the semiconductor device. The shield layer comprises an electrically conductive material. The method further comprises coupling the radio frequency field effect transistor to a circuit comprising a radio frequency component. The method further comprises singulating the radio frequency field effect transistor, radio frequency component, and the shield layer into a die. The shield layer is located between a substrate of the radio frequency component and the radio frequency field effect transistor.
-
9.
公开(公告)号:US09721832B2
公开(公告)日:2017-08-01
申请号:US13834329
申请日:2013-03-15
IPC分类号: H01L21/762 , H01L27/12 , H01L27/146 , H01L31/18 , H01L23/00
CPC分类号: H01L21/76256 , H01L21/7624 , H01L21/76251 , H01L24/80 , H01L27/1203 , H01L27/14687 , H01L31/1892 , H01L2221/68363 , H01L2224/80896
摘要: A method for fabricating silicon-on-insulator (SOI) semiconductor devices, wherein the piezoresistive pattern is defined within a blanket doped layer after fusion bonding. This new method of fabricating SOI semiconductor devices is more suitable for simpler large scale fabrication as it provides the flexibility to select the device pattern/type at the latest stages of fabrication.
-
公开(公告)号:US20170104084A1
公开(公告)日:2017-04-13
申请号:US15280214
申请日:2016-09-29
申请人: Semiconductor Manufacturing International (Beijing) Corporation , Semiconductor Manufacturing International (Shanghai) Corporation
发明人: HERB HE HUANG , CLIFFORD IAN DROWLEY , HAI TING LI , JI GUANG ZHU
IPC分类号: H01L29/66 , H01L21/311 , H01L21/306 , H01L29/786 , H01L21/762
CPC分类号: H01L29/66484 , H01L21/30625 , H01L21/31111 , H01L21/31116 , H01L21/76256 , H01L29/66742 , H01L29/78621 , H01L29/78648
摘要: The present disclosure provides a method for forming a transistor, including: forming a base structure, containing a first gate structure, an active layer covering the first gate structure, and an insulating structure in the active layer; forming a second gate structure on the active layer; forming a source-drain region, including a source region and a drain region in the active layer each on a different side of the second gate structure; and forming a first interlayer dielectric layer covering the base structure and the second gate structure. The method also includes: forming a first contact hole that exposes the first gate structure by etching the first interlayer dielectric layer and the insulating structure; and forming a second contact hole that exposes the second gate structure and a third contact hole that exposes the drain region by etching the first interlayer dielectric layer.
-
-
-
-
-
-
-
-
-