公开(公告)号：US20180096839A1

公开(公告)日：2018-04-05

申请号：US15284773

申请日：2016-10-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ryan Ryoung-Han KIM ,  Wenhui WANG ,  Azat LATYPOV ,  Tamer COSKUN ,  Lei SUN

IPC: H01L21/027 ,  H01L21/66 ,  H01L21/8234 ,  H01L21/306

CPC classification number: H01L21/0276 ,  H01L21/0337 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/823481 ,  H01L22/12 ,  H01L22/30

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method includes providing a circuit structure layer over a substrate and at least one etch layer over the circuit structure layer, in the at least one etch layer patterning at least one primary pattern feature having at least one primary pattern feature dimension and at least one assist pattern feature having at least one assist pattern feature dimension, where the primary pattern feature dimension is greater than the assist pattern feature dimension, reducing the at least one primary pattern feature dimension and closing the assist pattern feature to form an etch pattern, and etching a circuit structure feature using the etch pattern.