公开(公告)号：US20180076110A1

公开(公告)日：2018-03-15

申请号：US15264957

申请日：2016-09-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Rahul AGARWAL ,  Luke ENGLAND ,  Haojun ZHANG

IPC: H01L23/367 ,  H01L23/00 ,  H01L21/288

CPC classification number: H01L23/3675 ,  H01L21/2885 ,  H01L21/4871 ,  H01L23/3677 ,  H01L23/42 ,  H01L24/27 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/26122 ,  H01L2224/27011 ,  H01L2224/32245 ,  H01L2224/83007 ,  H01L2924/14

Abstract: Methods for reducing the junction temperature between an IC chip and its lid by including metal spacers in the TIM layer and the resulting devices are disclosed. Embodiments include providing a substrate, including integrated circuit devices, having front and back sides; forming vertical spacers on the backside of the substrate; providing a plate parallel to and spaced from the backside of the substrate; and forming a TIM layer, surrounding the vertical spacers, between the backside of the substrate and the plate.