公开(公告)号：US10396084B1

公开(公告)日：2019-08-27

申请号：US15944910

申请日：2018-04-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Nigel Chan ,  Nilesh Kenkare ,  Hongsik Yoon

IPC: H01L21/027 ,  H01L27/11 ,  H01L21/033 ,  H01L21/308

Abstract: Active regions for planar transistor architectures may be patterned in one lateral direction, i.e., the width direction, on the basis of a single lithography process, followed by deposition and etch processes, thereby providing multiple width dimensions and multiple spaces or pitches with reduced process variability due to the avoidance of overlay errors typically associated with conventional approaches when patterning the width dimensions and spaces on the basis of a sequence of sophisticated lithography processes. Consequently, increased packing density, enhanced performance and reduced manufacturing costs may be achieved on the basis of process techniques as disclosed herein.