公开(公告)号：US09847347B1

公开(公告)日：2017-12-19

申请号：US15344856

申请日：2016-11-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Nilesh Kenkare ,  Nigel Chan

IPC: H01L27/12 ,  H01L29/51 ,  H01L29/45 ,  H01L29/417 ,  H01L29/66 ,  H01L21/84 ,  H01L21/311

CPC classification number: H01L27/1203 ,  H01L21/31144 ,  H01L21/84 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/51 ,  H01L29/66545

Abstract: A semiconductor structure includes a substrate, a first transistor and a second transistor. The substrate includes a semiconductor-on-insulator region and a bulk region. The first transistor is provided at the semiconductor-on-insulator region and includes a first gate structure and a first channel region provided in a layer of semiconductor material over a layer of electrically insulating material. The second transistor is provided at the bulk region and includes a second gate structure and a second channel region provided in a bulk semiconductor material. A plane of an interface between the second channel region and the second gate structure is not above a plane of an interface between the bulk semiconductor material and the layer of electrically insulating material in the semiconductor-on-insulator region. A height of the second gate structure is greater than a height of the first gate structure.

公开(公告)号：US10418380B2

公开(公告)日：2019-09-17

申请号：US15664061

申请日：2017-07-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Nigel Chan ,  Nilesh Kenkare

IPC: H01L21/8234 ,  H01L27/12 ,  H01L21/84 ,  H01L21/266

Abstract: A method of forming a semiconductor device is provided including the steps of providing a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on the semiconductor bulk substrate and a semiconductor layer positioned on the buried insulation layer, and forming a first transistor device, wherein forming the first transistor device includes forming a channel region in the semiconductor bulk substrate and forming a gate insulation layer over the channel region partially of a part of the buried insulation layer and wherein forming the gate insulation layer includes oxidizing a part of the semiconductor layer.

公开(公告)号：US20190319048A1

公开(公告)日：2019-10-17

申请号：US16446906

申请日：2019-06-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Nigel Chan ,  Nilesh Kenkare

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/266

Abstract: One illustrative device disclosed herein is formed on an SOI substrate. The transistor device includes a first channel region formed in a semiconductor bulk substrate of the SOI substrate and a first gate insulation layer formed above the first channel region. In one embodiment, the first gate insulation layer includes a part of the buried insulation layer of the SOI substrate and an oxidized part of the semiconductor layer of the SOI substrate.

公开(公告)号：US10396084B1

公开(公告)日：2019-08-27

申请号：US15944910

申请日：2018-04-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Nigel Chan ,  Nilesh Kenkare ,  Hongsik Yoon

IPC: H01L21/027 ,  H01L27/11 ,  H01L21/033 ,  H01L21/308

Abstract: Active regions for planar transistor architectures may be patterned in one lateral direction, i.e., the width direction, on the basis of a single lithography process, followed by deposition and etch processes, thereby providing multiple width dimensions and multiple spaces or pitches with reduced process variability due to the avoidance of overlay errors typically associated with conventional approaches when patterning the width dimensions and spaces on the basis of a sequence of sophisticated lithography processes. Consequently, increased packing density, enhanced performance and reduced manufacturing costs may be achieved on the basis of process techniques as disclosed herein.

公开(公告)号：US10811433B2

公开(公告)日：2020-10-20

申请号：US16446906

申请日：2019-06-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Nigel Chan ,  Nilesh Kenkare

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/266 ,  H01L21/8234 ,  H01L21/8238

Abstract: One illustrative device disclosed herein is formed on an SOI substrate. The transistor device includes a first channel region formed in a semiconductor bulk substrate of the SOI substrate and a first gate insulation layer formed above the first channel region. In one embodiment, the first gate insulation layer includes a part of the buried insulation layer of the SOI substrate and an oxidized part of the semiconductor layer of the SOI substrate.

公开(公告)号：US20190035815A1

公开(公告)日：2019-01-31

申请号：US15664061

申请日：2017-07-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Nigel Chan ,  Nilesh Kenkare

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/266

CPC classification number: H01L27/1207 ,  H01L21/266 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/84

Abstract: A method of forming a semiconductor device is provided including the steps of providing a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on the semiconductor bulk substrate and a semiconductor layer positioned on the buried insulation layer, and forming a first transistor device, wherein forming the first transistor device includes forming a channel region in the semiconductor bulk substrate and forming a gate insulation layer over the channel region partially of a part of the buried insulation layer and wherein forming the gate insulation layer includes oxidizing a part of the semiconductor layer.