公开(公告)号：US10593674B1

公开(公告)日：2020-03-17

申请号：US16129221

申请日：2018-09-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ming-Cheng Chang ,  Nigel Chan ,  Elliot John Smith

IPC: H01L29/78 ,  H01L27/092 ,  H03K19/0948 ,  H01L21/762 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/06 ,  H01L27/088 ,  H01L27/02

Abstract: Structures for field-effect transistors and methods for fabricating a structure for field-effect transistors. A logic cell includes first and second field-effect transistors and a well defining a back gate that is arranged beneath the first and second field-effect transistors. A dielectric layer is arranged between the well and the logic cell. A plurality of deep trench isolation regions extend through the dielectric layer and are arranged to surround the first and second field-effect transistors and the well. The back gate is shared by the first and second field-effect transistors.

公开(公告)号：US10483154B1

公开(公告)日：2019-11-19

申请号：US16015351

申请日：2018-06-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Marcus Wolf ,  Carsten Peters ,  Markus Lenski ,  Loic Gaben

IPC: H01L21/762 ,  H01L21/02 ,  H01L29/06

Abstract: In various aspects, the present disclosure relates to device structures and a method of forming such a device structure. In some illustrative embodiments herein, a device is provided, including a semiconductor substrate having a first trench formed therein, and a first trench isolation structure formed in the first trench. The first trench isolation structure includes first and second insulating liners formed adjacent inner surfaces of the first trench, wherein the first insulating liner is in direct contact with inner surfaces of the first trench and the second insulating liner is formed directly on the first insulating liner, and a first insulating filling material which at least partially fills the first trench. In some aspects, a thickness of the first insulating liner is greater than a thickness of the second insulating liner.

公开(公告)号：US10319827B2

公开(公告)日：2019-06-11

申请号：US15647403

申请日：2017-07-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Nigel Chan

IPC: H01L29/51 ,  H01L29/165 ,  H01L29/66

Abstract: A high voltage transistor may be formed on the basis of well-established CMOS techniques by using a buried insulating material of an SOI architecture as gate dielectric material, while the gate electrode material may be provided in the form of a doped semiconductor region positioned below the buried insulating layer. The high voltage transistor may be formed with high process compatibility on the basis of a process flow for forming sophisticated fully depleted SOI transistors, wherein, in some illustrative embodiments, the high voltage transistor may also be provided as a fully depleted transistor configuration.

公开(公告)号：US20180175155A1

公开(公告)日：2018-06-21

申请号：US15889321

申请日：2018-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith

IPC: H01L29/51 ,  H01L29/66 ,  H01L21/308 ,  H01L29/417 ,  H01L29/06 ,  H01L29/786 ,  H01L21/306

CPC classification number: H01L29/51 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/32139 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/41783 ,  H01L29/42376 ,  H01L29/66484 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/786

Abstract: A high-k dielectric metal gate (HKMG) transistor includes a substrate, an HKMG gate stack with a gate dielectric layer and a gate electrode layer positioned above the substrate. The gate electrode layer has an upper portion and a lower portion. A first liner contacts a sidewall portion of the upper portion. A spacer contacts the first liner and a sidewall portion of the lower portion. Raised source and drain regions are positioned adjacent the spacer. A height of the uppermost surface of the spacer is greater than a height of an uppermost surface of the raised source and drain regions. A width of the upper portion between the raised source and drain regions is smaller than a width of the lower portion between the raised source and drain regions.

公开(公告)号：US09768084B1

公开(公告)日：2017-09-19

申请号：US15075378

申请日：2016-03-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Nigel Chan

IPC: H01L21/306 ,  H01L21/66 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/11 ,  H01L27/12

CPC classification number: H01L22/30 ,  H01L21/30604 ,  H01L21/823456 ,  H01L21/84 ,  H01L22/12 ,  H01L27/11 ,  H01L27/1203 ,  H01L29/4236

Abstract: In one aspect of the present disclosure, a method is provided, the method including providing a test region in an upper surface region of a semiconductor substrate, forming a plurality of trenches in the test region, the trenches of the plurality of trenches having at least one of a varying width, a varying length, and a varying bridge between adjacent trenches, determining depth values of the trenches, and evaluating the risk of defects of gate electrodes to be formed on the basis of the depth values.

公开(公告)号：US09633857B1

公开(公告)日：2017-04-25

申请号：US15087392

申请日：2016-03-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Steffen Sichler

IPC: H01L21/28 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/51 ,  H01L23/535 ,  H01L21/84 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L29/0649 ,  H01L21/28123 ,  H01L21/76224 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/66545

Abstract: A semiconductor structure includes a trench isolation structure, a trench capping layer, a gate structure and a sidewall spacer. The trench isolation structure includes a first electrically insulating material. The trench capping layer is provided over the trench isolation structure. The trench capping layer includes a second electrically insulating material that is different from the first electrically insulating material. The gate structure includes a gate insulation layer including a high-k material and a gate electrode over the gate insulation layer. The gate structure has a first portion over the trench capping layer. The sidewall spacer is provided adjacent the gate structure. A portion of the sidewall spacer is provided on the trench capping layer and contacts the trench capping layer laterally of the gate insulation layer.

公开(公告)号：US20170077314A1

公开(公告)日：2017-03-16

申请号：US14853146

申请日：2015-09-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Sven Beyer ,  Nigel Chan ,  Jan Hoentschel

IPC: H01L29/792 ,  H01L29/06 ,  H01L21/326 ,  H01L29/423 ,  H01L21/762 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/7923 ,  H01L21/326 ,  H01L21/76254 ,  H01L21/76264 ,  H01L21/76283 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/665 ,  H01L29/66833

Abstract: The present disclosure provides, in a first aspect, a semiconductor device structure, including an SOI substrate comprising a semiconductor base substrate, a buried insulating structure formed on the semiconductor base substrate and a semiconductor film formed on the buried insulating structure, wherein the buried insulating structure comprises a multilayer stack having a nitride layer interposed between two oxide layers. The semiconductor device structure further includes a semiconductor device formed in and above an active region of the SOI substrate, and a back bias contact which is electrically connected to the semiconductor base substrate below the semiconductor device.

Abstract translation: 本公开在第一方面提供一种半导体器件结构，其包括：SOI衬底，其包括半导体基底衬底，形成在半导体基底衬底上的掩埋绝缘结构和形成在掩埋绝缘结构上的半导体膜，其中所述埋入绝缘 结构包括具有介于两个氧化物层之间的氮化物层的多层堆叠。 半导体器件结构还包括形成在SOI衬底的有源区中和之上的半导体器件，以及在半导体器件下电连接到半导体基底衬底的反偏压接触。

公开(公告)号：US09590118B1

公开(公告)日：2017-03-07

申请号：US14853146

申请日：2015-09-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Sven Beyer ,  Nigel Chan ,  Jan Hoentschel

IPC: H01L29/76 ,  H01L29/792 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L21/762 ,  H01L21/326

CPC classification number: H01L29/7923 ,  H01L21/326 ,  H01L21/76254 ,  H01L21/76264 ,  H01L21/76283 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/665 ,  H01L29/66833

Abstract: The present disclosure provides, in a first aspect, a semiconductor device structure, including an SOI substrate comprising a semiconductor base substrate, a buried insulating structure formed on the semiconductor base substrate and a semiconductor film formed on the buried insulating structure, wherein the buried insulating structure comprises a multilayer stack having a nitride layer interposed between two oxide layers. The semiconductor device structure further includes a semiconductor device formed in and above an active region of the SOI substrate, and a back bias contact which is electrically connected to the semiconductor base substrate below the semiconductor device.

Abstract translation: 本公开在第一方面提供一种半导体器件结构，其包括：SOI衬底，其包括半导体基底衬底，形成在半导体基底衬底上的掩埋绝缘结构和形成在掩埋绝缘结构上的半导体膜，其中所述埋入绝缘 结构包括具有介于两个氧化物层之间的氮化物层的多层堆叠。 半导体器件结构还包括形成在SOI衬底的有源区中和之上的半导体器件，以及在半导体器件下电连接到半导体基底衬底的反偏压接触。

公开(公告)号：US20200251576A1

公开(公告)日：2020-08-06

申请号：US16854552

申请日：2020-04-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Juergen Thees ,  Peter Baars ,  Elliot John Smith

IPC: H01L29/66 ,  H01L21/308 ,  H01L21/762 ,  H01L21/306 ,  H01L27/12 ,  H01L29/786 ,  H01L21/285 ,  H01L29/423 ,  H01L29/49

Abstract: A device including an SOI substrate and an isolation structure positioned at least partially in a trench that extends through a buried insulation layer and into a semiconductor bulk substrate of the SOI substrate is disclosed. The isolation structure includes a first dielectric layer positioned in a lower portion of the trench, a first material layer positioned above the first dielectric layer, the first material layer having a material different from a material of the first dielectric layer, and a second dielectric layer positioned above the first material layer, the second dielectric layer having a material different from the material of the first material layer.

公开(公告)号：US20190319048A1

公开(公告)日：2019-10-17

申请号：US16446906

申请日：2019-06-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Nigel Chan ,  Nilesh Kenkare

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/266

Abstract: One illustrative device disclosed herein is formed on an SOI substrate. The transistor device includes a first channel region formed in a semiconductor bulk substrate of the SOI substrate and a first gate insulation layer formed above the first channel region. In one embodiment, the first gate insulation layer includes a part of the buried insulation layer of the SOI substrate and an oxidized part of the semiconductor layer of the SOI substrate.