公开(公告)号：US20200144365A1

公开(公告)日：2020-05-07

申请号：US16180486

申请日：2018-11-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： George R. MULFINGER ,  Timothy J. MCARDLE ,  Judson R. HOLT ,  Steffen A. SICHLER ,  Ömür I. AYDIN ,  Wei HONG ,  Yi QI ,  Hui ZANG ,  Liu JIANG

IPC: H01L29/08 ,  H01L21/8238 ,  H01L29/06 ,  H01L21/28 ,  H01L29/423

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to faceted epitaxial source/drain regions and methods of manufacture. The structure includes: a gate structure over a substrate; an L-shaped sidewall spacer located on sidewalls of the gate structure and extending over the substrate adjacent to the gate structure; and faceted diffusion regions on the substrate, adjacent to the L-shaped sidewall spacer.

公开(公告)号：US20180286982A1

公开(公告)日：2018-10-04

申请号：US15475873

申请日：2017-03-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bharat V. KRISHNAN ,  Timothy J. MCARDLE ,  Rinus Tek Po LEE ,  Shishir K. Ray ,  Akshey SEHGAL

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/45 ,  H01L27/092 ,  H01L29/66 ,  H01L21/265 ,  H01L21/8238

CPC classification number: H01L29/66795 ,  H01L29/41791 ,  H01L29/7848 ,  H01L2029/7858 ,  H01L2924/13067

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to finFETs with strained channels and reduced on state resistances and methods of manufacture. The structure includes: a plurality of fin structures comprising doped source and drain regions with a diffusion blocking layer between the doped source and drain regions and an underlying fin region formed within dielectric material.

公开(公告)号：US20190043967A1

公开(公告)日：2019-02-07

申请号：US16026820

申请日：2018-07-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George Robert MULFINGER ,  Ryan SPORER ,  Timothy J. MCARDLE ,  Judson Robert HOLT

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L27/12 ,  H01L21/02 ,  H01L21/84 ,  H01L21/225

Abstract: Methods of forming a graded SiGe percentage PFET channel in a FinFET or FDSOI device by post gate thermal condensation and oxidation of a high Ge percentage channel layer and the resulting devices are provided. Embodiments include forming a gate dielectric layer over a plurality of Si fins; forming a gate over each fin; forming a HM and spacer layer over and on sidewalls of each gate; forming a cavity in each fin adjacent to the gate and spacer layer; epitaxially growing an un-doped high percentage SiGe layer in each cavity and along sidewalls of each fin; thermally condensing the high percentage SiGe layer, an un-doped low percentage SiGe formed underneath in the substrate and fins; and forming a S/D region over the high percentage SiGe layer in each u-shaped cavity, an upper surface of the S/D regions below the gate dielectric layer.

公开(公告)号：US20180233505A1

公开(公告)日：2018-08-16

申请号：US15719014

申请日：2017-09-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George R. MULFINGER ,  Lakshmanan H. VANAMURTHY ,  Scott BEASOR ,  Timothy J. MCARDLE ,  Judson R. HOLT ,  Hao ZHANG

IPC: H01L27/092 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/165 ,  H01L21/02 ,  H01L29/167 ,  H01L21/285 ,  H01L29/66 ,  H01L21/265 ,  H01L29/45

Abstract: A method for forming a self-aligned sacrificial epitaxial cap for trench silicide and the resulting device are provided. Embodiments include a Si fin formed in a PFET region; a pair of Si fins formed in a NFET region; epitaxial S/D regions formed on ends of the Si fins; a replacement metal gate formed over the Si fins in the PFET and NFET regions; metal silicide trenches formed over the epitaxial S/D regions in the PFET and NEFT regions; a metal layer formed over top surfaces of the S/D region in the PFET region and top and bottom surfaces of the S/D regions in the NFET region, wherein the epitaxial S/D regions in the PFET and NFET regions are diamond shaped in cross-sectional view.

公开(公告)号：US20170294515A1

公开(公告)日：2017-10-12

申请号：US15609295

申请日：2017-05-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Timothy J. MCARDLE ,  Judson R. HOLT ,  Junli WANG

IPC: H01L29/161 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L29/10

CPC classification number: H01L29/161 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02494 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/04 ,  H01L29/045 ,  H01L29/10 ,  H01L29/1054 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: Semiconductor device fabrication method and structures are provided having a substrate structure which includes a silicon layer at an upper portion. The silicon layer is recessed in a first region of the substrate structure and remains unrecessed in a second region of the substrate structure. A protective layer having a first germanium concentration is formed above the recessed silicon layer in the first region, which extends along a sidewall of the unrecessed silicon layer of the second region. A semiconductor layer having a second germanium concentration is disposed above the protective layer in the first region of the substrate structure, where the first germanium concentration of the protective layer inhibits lateral diffusion of the second germanium concentration from the semiconductor layer in the first region into the unrecessed silicon layer in the second region of the substrate structure.