公开(公告)号：US20170330953A1

公开(公告)日：2017-11-16

申请号：US15151550

申请日：2016-05-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George Robert MULFINGER ,  Ryan SPORER ,  Rick J. CARTER ,  Peter BAARS ,  Hans-Jürgen THEES ,  Jan HÖNTSCHEL

IPC: H01L29/66 ,  H01L29/161 ,  H01L29/16 ,  H01L27/12 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/84 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L29/6656 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/7838

Abstract: A method of forming matched PFET/NFET spacers with differential widths for SG and EG structures and a method of forming differential width nitride spacers for SG NFET and SG PFET structures and PFET/NFET EG structures and respective resulting devices are provided. Embodiments include providing PFET SG and EG structures and NFET SG and EG structures; forming a first nitride layer over the substrate; forming an oxide liner; forming a second nitride layer on sidewalls of the PFET and NFET EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the PFET SG and EG structures; forming RSD structures on opposite sides of each of the PFET SG and EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the NFET SG and EG structures; and forming RSD structures on opposite sides of each of the NFET SG and EG structures.

公开(公告)号：US20180069091A1

公开(公告)日：2018-03-08

申请号：US15256027

申请日：2016-09-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George Robert MULFINGER ,  Dina H. TRIYOSO ,  Ryan SPORER

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/51 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L29/66545 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/41783 ,  H01L29/517 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/786

Abstract: Methods for selectively thinning a silicon channel area under a gate electrode and resulting devices are disclosed. Embodiments include providing a SOI substrate including a Si-layer; providing a first dummy-gate electrode over a first gate-oxide between first spacers over a first channel area of the Si-layer and a second dummy-gate electrode over a second gate-oxide between second spacers over a second channel area of the Si-layer; forming a S/D region adjacent each spacer; forming an oxide over the S/D regions and the spacers; removing the dummy-gate electrodes creating first and second cavities between respective first and second spacers; forming a mask with an opening over the first cavity; removing the first gate-oxide; thinning the Si-layer under the first cavity, forming a recess in the Si-layer; forming a third gate-oxide on recess side and bottom surfaces; and filling the recess and the cavities with metal, forming first and second RMG electrodes.

公开(公告)号：US20190043967A1

公开(公告)日：2019-02-07

申请号：US16026820

申请日：2018-07-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George Robert MULFINGER ,  Ryan SPORER ,  Timothy J. MCARDLE ,  Judson Robert HOLT

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L27/12 ,  H01L21/02 ,  H01L21/84 ,  H01L21/225

Abstract: Methods of forming a graded SiGe percentage PFET channel in a FinFET or FDSOI device by post gate thermal condensation and oxidation of a high Ge percentage channel layer and the resulting devices are provided. Embodiments include forming a gate dielectric layer over a plurality of Si fins; forming a gate over each fin; forming a HM and spacer layer over and on sidewalls of each gate; forming a cavity in each fin adjacent to the gate and spacer layer; epitaxially growing an un-doped high percentage SiGe layer in each cavity and along sidewalls of each fin; thermally condensing the high percentage SiGe layer, an un-doped low percentage SiGe formed underneath in the substrate and fins; and forming a S/D region over the high percentage SiGe layer in each u-shaped cavity, an upper surface of the S/D regions below the gate dielectric layer.

公开(公告)号：US20180012973A1

公开(公告)日：2018-01-11

申请号：US15711674

申请日：2017-09-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George Robert MULFINGER ,  Ryan SPORER ,  Rick J. CARTER ,  Peter BAARS ,  Hans-Jürgen THEES ,  Jan HÖNTSCHEL

IPC: H01L29/66 ,  H01L29/161 ,  H01L29/16 ,  H01L27/12 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/84 ,  H01L29/78 ,  H01L29/08

Abstract: A method of forming matched PFET/NFET spacers with differential widths for SG and EG structures and a method of forming differential width nitride spacers for SG NFET and SG PFET structures and PFET/NFET EG structures and respective resulting devices are provided. Embodiments include providing PFET SG and EG structures and NFET SG and EG structures; forming a first nitride layer over the substrate; forming an oxide liner; forming a second nitride layer on sidewalls of the PFET and NFET EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the PFET SG and EG structures; forming RSD structures on opposite sides of each of the PFET SG and EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the NFET SG and EG structures; and forming RSD structures on opposite sides of each of the NFET SG and EG structures.

公开(公告)号：US20200083346A1

公开(公告)日：2020-03-12

申请号：US16680196

申请日：2019-11-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George Robert MULFINGER ,  Ryan SPORER ,  Rick J. CARTER ,  Peter BAARS ,  Hans-Jürgen THEES ,  Jan HÖNTSCHEL

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78

Abstract: A method of forming matched PFET/NFET spacers with differential widths for SG and EG structures and a method of forming differential width nitride spacers for SG NFET and SG PFET structures and PFET/NFET EG structures and respective resulting devices are provided. Embodiments include providing PFET SG and EG structures and NFET SG and EG structures; forming a first nitride layer over the substrate; forming an oxide liner; forming a second nitride layer on sidewalls of the PFET and NFET EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the PFET SG and EG structures; forming RSD structures on opposite sides of each of the PFET SG and EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the NFET SG and EG structures; and forming RSD structures on opposite sides of each of the NFET SG and EG structures.

公开(公告)号：US20180315832A1

公开(公告)日：2018-11-01

申请号：US16028082

申请日：2018-07-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George Robert MULFINGER ,  Dina H. TRIYOSO ,  Ryan SPORER

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/84 ,  H01L27/12 ,  H01L29/417 ,  H01L29/06 ,  H01L29/51

CPC classification number: H01L29/66545 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/41783 ,  H01L29/517 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/786

Abstract: Methods for selectively thinning a silicon channel area under a gate electrode and resulting devices are disclosed. Embodiments include providing a SOI substrate including a Si-layer; providing a first dummy-gate electrode over a first gate-oxide between first spacers over a first channel area of the Si-layer and a second dummy-gate electrode over a second gate-oxide between second spacers over a second channel area of the Si-layer; forming a S/D region adjacent each spacer; forming an oxide over the S/D regions and the spacers; removing the dummy-gate electrodes creating first and second cavities between respective first and second spacers; forming a mask with an opening over the first cavity; removing the first gate-oxide; thinning the Si-layer under the first cavity, forming a recess in the Si-layer; forming a third gate-oxide on recess side and bottom surfaces; and filling the recess and the cavities with metal, forming first and second RMG electrodes.

公开(公告)号：US20180130712A1

公开(公告)日：2018-05-10

申请号：US15839243

申请日：2017-12-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ryan SPORER ,  Rohit PAL ,  Jeremy WAHL

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/092 ,  H01L21/3105 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/088

CPC classification number: H01L21/823431 ,  H01L21/31053 ,  H01L21/76224 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/6653 ,  H01L29/66795

Abstract: Methods for forming fins with a straight profile by preventing fin bending during STI fill and annealing are disclosed. Embodiments include providing STI regions separated by Si regions, each topped with a hardmask; planarizing the STI regions; removing the hardmask over a portion of the Si regions, forming recesses; forming a conformal spacer layer over the STI regions and in the recesses; removing horizontal portions of the spacer layer; epitaxially growing Si in each recess, forming fins; and etching the STI regions and a remainder of the spacer layer down to the Si regions to reveal the fins.