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1.发明授权Methods involving pattern matching to identify and resolve potential non-double-patterning-compliant patterns in double patterning applications 有权涉及模式匹配的方法来识别和解决双重图案化应用中潜在的非双重图案化兼容图案公开(公告)号：US08910090B2
公开(公告)日：2014-12-09
申请号：US13778322
申请日：2013-02-27
Applicant: GLOBALFOUNDRIES Inc.
Inventor： Lynn T. Wang , Vito Dai , Luigi Capodieci
IPC: G06F17/50
CPC classification number: G06F17/5081 , G06F2217/12 , Y02P90/265
Abstract: One illustrative method disclosed herein involves producing an initial circuit layout, prior to decomposing the initial circuit layout, identifying at least one potential non-double-patterning-compliant (NDPC) pattern in the initial circuit layout, fixing the at least one potential non-double-patterning-compliant (NDPC) pattern so as to produce a double-patterning-compliant (DPT) pattern, producing a modified circuit layout by removing the potential non-double-patterning-compliant (NDPC) pattern and adding the double-patterning-compliant (DPT) pattern to the initial circuit layout, and performing design rule checking and double patterning compliance checking on the modified circuit layout.
Abstract translation: 本文公开的一种说明性方法涉及在分解初始电路布局之前产生初始电路布局，在初始电路布局中识别至少一个潜在的非双图案化兼容（NDPC）图案， 双图案化（NDPC）图案，以产生双图案化（DPT）图案，通过去除潜在的非双重图案化兼容（NDPC）图案并添加双图案化（DPI）图案，从而产生修改的电路布局 （DPT）模式，并对修改的电路布局执行设计规则检查和双重图案化合规检查。
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2.发明申请METHODS INVOLVING PATTERN MATCHING TO IDENTIFY AND RESOLVE POTENTIAL NON-DOUBLE-PATTERNING-COMPLIANT PATTERNS IN DOUBLE PATTERNING APPLICATIONS 有权涉及图案匹配的方法来识别和解决双重文件应用中的潜在非双向拼写图案公开(公告)号：US20140245238A1
公开(公告)日：2014-08-28
申请号：US13778322
申请日：2013-02-27
Applicant: GLOBALFOUNDRIES INC.
Inventor： Lynn T. Wang , Vito Dai , Luigi Capodieci
IPC: G06F17/50
CPC classification number: G06F17/5081 , G06F2217/12 , Y02P90/265
Abstract: One illustrative method disclosed herein involves producing an initial circuit layout, prior to decomposing the initial circuit layout, identifying at least one potential non-double-patterning-compliant (NDPC) pattern in the initial circuit layout, fixing the at least one potential non-double-patterning-compliant (NDPC) pattern so as to produce a double-patterning-compliant (DPT) pattern, producing a modified circuit layout by removing the potential non-double-patterning-compliant (NDPC) pattern and adding the double-patterning-compliant (DPT) pattern to the initial circuit layout, and performing design rule checking and double patterning compliance checking on the modified circuit layout.
Abstract translation: 本文公开的一种说明性方法涉及在分解初始电路布局之前产生初始电路布局，在初始电路布局中识别至少一个潜在的非双图案化兼容（NDPC）图案， 双图案化（NDPC）图案，以产生双图案化（DPT）图案，通过去除潜在的非双重图案化兼容（NDPC）图案并添加双图案化（DPI）图案，从而产生修改的电路布局 （DPT）模式，并对修改的电路布局执行设计规则检查和双重图案化合规检查。
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