公开(公告)号：US20150012896A1

公开(公告)日：2015-01-08

申请号：US13936910

申请日：2013-07-08

Applicant: Globalfoundries, Inc.

Inventor： Azat Latypov ,  Yi Zou ,  Vito Dai

IPC: G03F7/20

CPC classification number: G03F7/70441 ,  B82Y30/00

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating a photomask for forming a DSA directing pattern on a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the photomask includes, using a computing system, inputting a DSA target pattern. Using the computing system, a DSA model, an OPC model, and a MPC model, cooperatively running a DSA PC algorithm, an OPC algorithm, and a MPC algorithm to produce an output MPCed pattern for a mask writer to write on the photomask.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，制造集成电路的方法包括产生用于在半导体衬底上形成DSA定向图案的光掩模。 DSA引导图案被配置为引导沉积在其上的自组装材料经历定向自组装（DSA）以形成DSA图案。 生成光掩模包括使用计算系统输入DSA目标图案。 使用计算系统，DSA模型，OPC模型和MPC模型，协作运行DSA PC算法，OPC算法和MPC算法，以产生用于掩模写入器在光掩模上写入的输出MPCed模式。

公开(公告)号：US09023730B1

公开(公告)日：2015-05-05

申请号：US14072164

申请日：2013-11-05

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Azat Latypov ,  Yi Zou ,  Vito Dai

IPC: H01L21/311 ,  G06F17/50 ,  H01L21/027 ,  H01L21/033

CPC classification number: H01L21/0337 ,  H01L21/0273

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating an e-beam pattern for forming a DSA directing pattern on a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the e-beam pattern includes using a computing system, inputting a DSA target pattern. Using the computing system, the DSA target pattern, a DSA model, and an EBPC model, an output EBPCed pattern is produced for an e-beam writer to write on a resist layer that overlies the semiconductor substrate.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，用于制造集成电路的方法包括产生用于在半导体衬底上形成DSA定向图案的电子束图案。 DSA引导图案被配置为引导沉积在其上的自组装材料经历定向自组装（DSA）以形成DSA图案。 生成电子束图案包括使用计算系统，输入DSA目标图案。 使用计算系统，DSA目标模式，DSA模型和EBPC模型，产生用于电子束写入器写入覆盖在半导体衬底上的抗蚀剂层上的输出EBPC模式。

公开(公告)号：US08910090B2

公开(公告)日：2014-12-09

申请号：US13778322

申请日：2013-02-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lynn T. Wang ,  Vito Dai ,  Luigi Capodieci

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

Abstract: One illustrative method disclosed herein involves producing an initial circuit layout, prior to decomposing the initial circuit layout, identifying at least one potential non-double-patterning-compliant (NDPC) pattern in the initial circuit layout, fixing the at least one potential non-double-patterning-compliant (NDPC) pattern so as to produce a double-patterning-compliant (DPT) pattern, producing a modified circuit layout by removing the potential non-double-patterning-compliant (NDPC) pattern and adding the double-patterning-compliant (DPT) pattern to the initial circuit layout, and performing design rule checking and double patterning compliance checking on the modified circuit layout.

Abstract translation: 本文公开的一种说明性方法涉及在分解初始电路布局之前产生初始电路布局，在初始电路布局中识别至少一个潜在的非双图案化兼容（NDPC）图案， 双图案化（NDPC）图案，以产生双图案化（DPT）图案，通过去除潜在的非双重图案化兼容（NDPC）图案并添加双图案化（DPI）图案，从而产生修改的电路布局 （DPT）模式，并对修改的电路布局执行设计规则检查和双重图案化合规检查。

公开(公告)号：US20140245238A1

公开(公告)日：2014-08-28

申请号：US13778322

申请日：2013-02-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lynn T. Wang ,  Vito Dai ,  Luigi Capodieci

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

Abstract: One illustrative method disclosed herein involves producing an initial circuit layout, prior to decomposing the initial circuit layout, identifying at least one potential non-double-patterning-compliant (NDPC) pattern in the initial circuit layout, fixing the at least one potential non-double-patterning-compliant (NDPC) pattern so as to produce a double-patterning-compliant (DPT) pattern, producing a modified circuit layout by removing the potential non-double-patterning-compliant (NDPC) pattern and adding the double-patterning-compliant (DPT) pattern to the initial circuit layout, and performing design rule checking and double patterning compliance checking on the modified circuit layout.

Abstract translation: 本文公开的一种说明性方法涉及在分解初始电路布局之前产生初始电路布局，在初始电路布局中识别至少一个潜在的非双图案化兼容（NDPC）图案， 双图案化（NDPC）图案，以产生双图案化（DPT）图案，通过去除潜在的非双重图案化兼容（NDPC）图案并添加双图案化（DPI）图案，从而产生修改的电路布局 （DPT）模式，并对修改的电路布局执行设计规则检查和双重图案化合规检查。

公开(公告)号：US09009634B2

公开(公告)日：2015-04-14

申请号：US13936910

申请日：2013-07-08

Applicant: GlobalFoundries, Inc.

Inventor： Azat Latypov ,  Yi Zou ,  Vito Dai

IPC: G06F17/50 ,  G03F7/20

CPC classification number: G03F7/70441 ,  B82Y30/00

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating a photomask for forming a DSA directing pattern on a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the photomask includes, using a computing system, inputting a DSA target pattern. Using the computing system, a DSA model, an OPC model, and a MPC model, cooperatively running a DSA PC algorithm, an OPC algorithm, and a MPC algorithm to produce an output MPCed pattern for a mask writer to write on the photomask.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，制造集成电路的方法包括产生用于在半导体衬底上形成DSA定向图案的光掩模。 DSA引导图案被配置为引导沉积在其上的自组装材料经历定向自组装（DSA）以形成DSA图案。 生成光掩模包括使用计算系统输入DSA目标图案。 使用计算系统，DSA模型，OPC模型和MPC模型，协作运行DSA PC算法，OPC算法和MPC算法，以产生用于掩模写入器在光掩模上写入的输出MPCed模式。

公开(公告)号：US08898606B1

公开(公告)日：2014-11-25

申请号：US14080866

申请日：2013-11-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Rani Abou Ghaida ,  Ahmed Mohyeldin ,  Piyush Pathak ,  Swamy Muddu ,  Vito Dai ,  Luigi Capodieci

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5077 ,  Y02T10/82

Abstract: A process and apparatus are provided for automated pattern-based semiconductor design layout correction. Embodiments include: determining a portion of a layout of an IC design, the portion comprising a first pattern of a plurality of routes connecting a plurality of design connections; determining one or more sets of the plurality of design connections based on the plurality of routes; and determining, by a processor, a second pattern of a plurality of routes connecting the plurality of design connections within the portion based on the one or more sets.

Abstract translation: 提供了一种用于基于自动图案的半导体设计布局校正的工艺和装置。 实施例包括：确定IC设计的布局的一部分，该部分包括连接多个设计连接的多条路线的第一模式; 基于所述多个路由确定所述多个设计连接的一个或多个集合; 以及由处理器确定基于所述一个或多个集合来连接所述部分内的所述多个设计连接的多条路线的第二模式。

公开(公告)号：US09170501B2

公开(公告)日：2015-10-27

申请号：US13936924

申请日：2013-07-08

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Azat Latypov ,  Yi Zou ,  Vito Dai

IPC: G06F17/50 ,  G03F7/20

CPC classification number: G03F7/70441 ,  G03F1/36 ,  G03F1/70 ,  G03F7/0002

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating a photomask for forming a DSA directing pattern on a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the photomask includes using a computing system, inputting a DSA target pattern and an initial pattern. An output mask writer pattern is produced from the initial pattern using the computing system, the DSA target pattern, a DSA model, an OPC model, and a MPC model. The output mask writer pattern is for a mask writer to write on the photomask.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，制造集成电路的方法包括产生用于在半导体衬底上形成DSA定向图案的光掩模。 DSA引导图案被配置为引导沉积在其上的自组装材料经历定向自组装（DSA）以形成DSA图案。 生成光掩模包括使用计算系统，输入DSA目标图案和初始图案。 使用计算系统，DSA目标模式，DSA模型，OPC模型和MPC模型从初始模式生成输出掩码写入器模式。 输出掩码写入器模式用于掩码写入器写入光掩模。