公开(公告)号：US20180233401A1

公开(公告)日：2018-08-16

申请号：US15951557

申请日：2018-04-12

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Steven M. Shank ,  Michel Abou-Khalil

IPC: H01L21/762 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L21/76286 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

Abstract: A trap-rich polysilicon layer is interposed between the active (SOI) layer and the underlying handle portion of a semiconductor substrate to prevent or minimize parasitic surface conduction effects within the active layer and promote device linearity. In various embodiments, the trap-rich layer extends vertically through a portion of an isolation layer and laterally therefrom between the isolation layer and the handle portion of the substrate to underlie a portion of the device active area.

公开(公告)号：US20180096884A1

公开(公告)日：2018-04-05

申请号：US15281418

申请日：2016-09-30

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Steven M. Shank ,  Michel Abou-Khalil

IPC: H01L21/762 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L21/76286 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

Abstract: A trap-rich polysilicon layer is interposed between the active (SOI) layer and the underlying handle portion of a semiconductor substrate to prevent or minimize parasitic surface conduction effects within the active layer and promote device linearity. In various embodiments, the trap-rich layer extends vertically through a portion of an isolation layer and laterally therefrom between the isolation layer and the handle portion of the substrate to underlie a portion of the device active area.

公开(公告)号：US10446435B2

公开(公告)日：2019-10-15

申请号：US15951557

申请日：2018-04-12

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Steven M. Shank ,  Michel Abou-Khalil

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84

Abstract: A trap-rich polysilicon layer is interposed between the active (SOI) layer and the underlying handle portion of a semiconductor substrate to prevent or minimize parasitic surface conduction effects within the active layer and promote device linearity. In various embodiments, the trap-rich layer extends vertically through a portion of an isolation layer and laterally therefrom between the isolation layer and the handle portion of the substrate to underlie a portion of the device active area.

公开(公告)号：US10062711B2

公开(公告)日：2018-08-28

申请号：US15386507

申请日：2016-12-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven Shank ,  Alvin Joseph ,  Michel Abou-Khalil ,  Michael Zierak

IPC: H01L27/12 ,  H01L21/00 ,  H01L21/84 ,  H01L29/06 ,  H01L23/528 ,  H01L29/423 ,  H01L21/762 ,  H01L21/683

CPC classification number: H01L27/1203 ,  H01L21/6835 ,  H01L21/76283 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/4238 ,  H01L29/42384 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78654 ,  H01L29/78696 ,  H01L2221/6835

Abstract: Wafers for fabrication of devices that include a body contact, device structures with a body contact, methods for forming a wafer that supports the fabrication of devices that include a body contact, and methods for forming a device structure that includes a body contact. The wafer includes a buried oxide layer and a semiconductor layer on the buried oxide layer. The semiconductor layer includes a section with a top surface and a plurality of islands projecting from the section of the semiconductor layer into the buried oxide layer. The section of the semiconductor layer is located vertically between the islands of the semiconductor layer and the top surface of the semiconductor layer.

公开(公告)号：US20180175064A1

公开(公告)日：2018-06-21

申请号：US15386507

申请日：2016-12-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven Shank ,  Alvin Joseph ,  Michel Abou-Khalil ,  Michael Zierak

IPC: H01L27/12 ,  H01L29/06 ,  H01L23/528 ,  H01L29/423 ,  H01L21/762 ,  H01L21/84 ,  H01L21/683

CPC classification number: H01L27/1203 ,  H01L21/6835 ,  H01L21/76283 ,  H01L21/84 ,  H01L23/528 ,  H01L29/0649 ,  H01L29/4238 ,  H01L2221/6835

Abstract: Wafers for fabrication of devices that include a body contact, device structures with a body contact, methods for forming a wafer that supports the fabrication of devices that include a body contact, and methods for forming a device structure that includes a body contact. The wafer includes a buried oxide layer and a semiconductor layer on the buried oxide layer. The semiconductor layer includes a section with a top surface and a plurality of islands projecting from the section of the semiconductor layer into the buried oxide layer. The section of the semiconductor layer is located vertically between the islands of the semiconductor layer and the top surface of the semiconductor layer.

公开(公告)号：US09991155B2

公开(公告)日：2018-06-05

申请号：US15281418

申请日：2016-09-30

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Steven M. Shank ,  Michel Abou-Khalil

IPC: H01L21/762 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L21/76286 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

Abstract: A trap-rich polysilicon layer is interposed between the active (SOI) layer and the underlying handle portion of a semiconductor substrate to prevent or minimize parasitic surface conduction effects within the active layer and promote device linearity. In various embodiments, the trap-rich layer extends vertically through a portion of an isolation layer and laterally therefrom between the isolation layer and the handle portion of the substrate to underlie a portion of the device active area.