公开(公告)号：US20170221882A1

公开(公告)日：2017-08-03

申请号：US15013411

申请日：2016-02-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ananth Sundaram ,  Balaji Swaminathan ,  Srikumar Konduru ,  Alvin Joseph ,  Michael Zierak

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/528

CPC classification number: H01L27/088 ,  H01L21/823418 ,  H01L21/823475 ,  H01L23/522 ,  H01L23/528 ,  H01L27/0207

Abstract: Chip structures having wiring coupled with the device structures of a high frequency switch and methods for fabricating such chip structures. A transistor is formed that includes a first source/drain region, a second source/drain region, and a first gate electrode having a first width aligned in a first direction. A wiring level is formed that includes a wire coupled with the first source/drain region. The wire has a length aligned in a second direction that is different from the first direction.

公开(公告)号：US20190273132A1

公开(公告)日：2019-09-05

申请号：US15911831

申请日：2018-03-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Michael Zierak ,  Anthony K. Stamper ,  John J. Pekarik ,  Vibhor Jain

IPC: H01L29/06 ,  H01L23/48 ,  H01L21/764 ,  H01L21/762 ,  H01L21/768

Abstract: Structures that include an airgap and methods for forming a structure that includes an airgap. A layer stack is epitaxially grown on a substrate and includes a first semiconductor layer and a second semiconductor layer on a substrate. A plurality of openings are formed that extend through a device region of the first semiconductor layer to the second semiconductor layer. The second semiconductor layer is etched through the openings and selective to the substrate and the first semiconductor layer so as to form an airgap that is arranged in a vertical direction between the substrate and the device region. A device structure is formed in the device region of the first semiconductor layer.

公开(公告)号：US10388728B1

公开(公告)日：2019-08-20

申请号：US15911831

申请日：2018-03-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Michael Zierak ,  Anthony K. Stamper ,  John J. Pekarik ,  Vibhor Jain

IPC: H01L29/06 ,  H01L23/48 ,  H01L21/768 ,  H01L21/762 ,  H01L21/764

Abstract: Structures that include an airgap and methods for forming a structure that includes an airgap. A layer stack is epitaxially grown on a substrate and includes a first semiconductor layer and a second semiconductor layer on a substrate. A plurality of openings are formed that extend through a device region of the first semiconductor layer to the second semiconductor layer. The second semiconductor layer is etched through the openings and selective to the substrate and the first semiconductor layer so as to form an airgap that is arranged in a vertical direction between the substrate and the device region. A device structure is formed in the device region of the first semiconductor layer.

公开(公告)号：US09721948B1

公开(公告)日：2017-08-01

申请号：US15013411

申请日：2016-02-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ananth Sundaram ,  Balaji Swaminathan ,  Srikumar Konduru ,  Alvin Joseph ,  Michael Zierak

IPC: H01L27/088 ,  H01L23/528 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/823418 ,  H01L21/823475 ,  H01L23/522 ,  H01L23/528 ,  H01L27/0207

Abstract: Chip structures having wiring coupled with the device structures of a high frequency switch and methods for fabricating such chip structures. A transistor is formed that includes a first source/drain region, a second source/drain region, and a first gate electrode having a first width aligned in a first direction. A wiring level is formed that includes a wire coupled with the first source/drain region. The wire has a length aligned in a second direction that is different from the first direction.

公开(公告)号：US10062711B2

公开(公告)日：2018-08-28

申请号：US15386507

申请日：2016-12-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven Shank ,  Alvin Joseph ,  Michel Abou-Khalil ,  Michael Zierak

IPC: H01L27/12 ,  H01L21/00 ,  H01L21/84 ,  H01L29/06 ,  H01L23/528 ,  H01L29/423 ,  H01L21/762 ,  H01L21/683

CPC classification number: H01L27/1203 ,  H01L21/6835 ,  H01L21/76283 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/4238 ,  H01L29/42384 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78654 ,  H01L29/78696 ,  H01L2221/6835

Abstract: Wafers for fabrication of devices that include a body contact, device structures with a body contact, methods for forming a wafer that supports the fabrication of devices that include a body contact, and methods for forming a device structure that includes a body contact. The wafer includes a buried oxide layer and a semiconductor layer on the buried oxide layer. The semiconductor layer includes a section with a top surface and a plurality of islands projecting from the section of the semiconductor layer into the buried oxide layer. The section of the semiconductor layer is located vertically between the islands of the semiconductor layer and the top surface of the semiconductor layer.

公开(公告)号：US20180175064A1

公开(公告)日：2018-06-21

申请号：US15386507

申请日：2016-12-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven Shank ,  Alvin Joseph ,  Michel Abou-Khalil ,  Michael Zierak

IPC: H01L27/12 ,  H01L29/06 ,  H01L23/528 ,  H01L29/423 ,  H01L21/762 ,  H01L21/84 ,  H01L21/683

CPC classification number: H01L27/1203 ,  H01L21/6835 ,  H01L21/76283 ,  H01L21/84 ,  H01L23/528 ,  H01L29/0649 ,  H01L29/4238 ,  H01L2221/6835

Abstract: Wafers for fabrication of devices that include a body contact, device structures with a body contact, methods for forming a wafer that supports the fabrication of devices that include a body contact, and methods for forming a device structure that includes a body contact. The wafer includes a buried oxide layer and a semiconductor layer on the buried oxide layer. The semiconductor layer includes a section with a top surface and a plurality of islands projecting from the section of the semiconductor layer into the buried oxide layer. The section of the semiconductor layer is located vertically between the islands of the semiconductor layer and the top surface of the semiconductor layer.