INTEGRATING OPTIMAL PLANAR AND THREE-DIMENSIONAL SEMICONDUCTOR DESIGN LAYOUTS
    1.
    发明申请
    INTEGRATING OPTIMAL PLANAR AND THREE-DIMENSIONAL SEMICONDUCTOR DESIGN LAYOUTS 有权
    集成最优平面和三维半导体设计层

    公开(公告)号:US20140258960A1

    公开(公告)日:2014-09-11

    申请号:US13792946

    申请日:2013-03-11

    CPC classification number: G06F17/5072 Y02T10/82

    Abstract: An approach and apparatus are provided for optimizing and combining different semiconductor technologies into a single graphic data system. Embodiments include generating a planar semiconductor layout design, generating a three-dimensional (e.g., FinFET) semiconductor layout design, and combining the planar design and the FinFET design in a common graphic data system.

    Abstract translation: 提供了将不同半导体技术优化并组合成单个图形数据系统的方法和装置。 实施例包括生成平面半导体布局设计,产生三维(例如,FinFET)半导体布局设计,以及将平面设计和FinFET设计组合在通用图形数据系统中。

    Parameterized cell for planar and finFET technology design
    2.
    发明授权
    Parameterized cell for planar and finFET technology design 有权
    用于平面和finFET技术设计的参数化单元

    公开(公告)号:US08904324B2

    公开(公告)日:2014-12-02

    申请号:US13836057

    申请日:2013-03-15

    CPC classification number: G06F17/5068 G06F17/505 H01L29/66795

    Abstract: A parameterized cell for planar and finFET designs is provided. A parameterized cell (Pcell) describing a planar design is integrated with fin-based design criteria, including fin pitch. For material regions in a planar design that have a corresponding region in a fin design, a quantized value based on the fin pitch is computed. The material can include regions such as active area silicon, contact regions, and local interconnect regions.

    Abstract translation: 提供了用于平面和finFET设计的参数化单元。 描述平面设计的参数化单元(Pcell)集成了基于翅片的设计标准,包括翅片间距。 对于在翅片设计中具有对应区域的平面设计中的材料区域,计算基于翅片间距的量化值。 该材料可以包括诸如有源区硅,接触区域和局部互连区域的区域。

    PARAMETERIZED CELL FOR PLANAR AND FINFET TECHNOLOGY DESIGN
    3.
    发明申请
    PARAMETERIZED CELL FOR PLANAR AND FINFET TECHNOLOGY DESIGN 有权
    用于平面和FinFET技术设计的参数化单元

    公开(公告)号:US20140282323A1

    公开(公告)日:2014-09-18

    申请号:US13836057

    申请日:2013-03-15

    CPC classification number: G06F17/5068 G06F17/505 H01L29/66795

    Abstract: A parameterized cell for planar and finFET designs is provided. A parameterized cell (Pcell) describing a planar design is integrated with fin-based design criteria, including fin pitch. For material regions in a planar design that have a corresponding region in a fin design, a quantized value based on the fin pitch is computed. The material can include regions such as active area silicon, contact regions, and local interconnect regions.

    Abstract translation: 提供了用于平面和finFET设计的参数化单元。 描述平面设计的参数化单元(Pcell)集成了基于翅片的设计标准,包括翅片间距。 对于在翅片设计中具有对应区域的平面设计中的材料区域,计算基于翅片间距的量化值。 该材料可以包括诸如有源区硅,接触区域和局部互连区域的区域。

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