公开(公告)号：US20210013150A1

公开(公告)日：2021-01-14

申请号：US17039187

申请日：2020-09-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mahbub Rashed ,  Irene Y. Lin ,  Steven Soss ,  Jeff Kim ,  Chinh Nguyen ,  Marc Tarabbia ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC: H01L23/535 ,  H01L21/8234 ,  H01L27/02 ,  H01L21/768 ,  H01L21/285 ,  H01L21/8238 ,  H01L23/532 ,  H01L27/092 ,  H01L29/08

Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate. The first transistor and a second transistor are formed on the semiconductor substrate. Each transistor comprises a source, a drain, and a gate. The gate of the first transistor extends longitudinally as part of a first linear strip and the gate of the second transistor extends longitudinally as part of the second linear strip parallel to and spaced apart from the first linear strip. A first CB layer forms a local interconnect layer electrically connected to the gate of the first transistor. A second CB layer forms a local interconnect layer electrically connected to the gate of the second transistor. A CA layer forms a local interconnect layer extending longitudinally between a first end and a second end of the CA layer. The CA layer is electrically connected to the first and second CB layers. The first CB layer is electrically connected adjacent the first end of the CA layer and the second layer is electrically connected adjacent the second end of the CA layer. The first CB layer, the second CB layer and the CA layer are disposed between a first metal layer and the semiconductor substrate. The first metal layer being disposed above each source, each drain, and each gate of the first and second transistors. The CA layer extends substantially parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers. At least one via selectively provides an electrical connection between the CA or CB layers and the at least one metal layer.

公开(公告)号：US20190148245A1

公开(公告)日：2019-05-16

申请号：US15810557

申请日：2017-11-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Rick Carter ,  Vikrant Chauhan ,  George Jonathan Kluth ,  Anurag Mittal ,  David Pritchard ,  Mahbub Rashed

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/417 ,  H01L27/12 ,  H01L29/49

CPC classification number: H01L21/823871 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/41783 ,  H01L29/4941 ,  H01L2924/0002

Abstract: A method of forming contacts includes forming a plurality of transistor devices separated by shallow trench insulator regions, the transistor devices each comprising a semiconductor substrate, a buried insulator layer on the semiconductor bulk substrate, a semiconductor layer on the buried insulator layer, a high-k metal gate stack on the semiconductor layer and a gate electrode above the high-k metal gate stack, raised source/drain regions on the semiconductor layer, and a silicide contact layer above the raised source/drain regions and the gate electrode, providing an interlayer dielectric stack on the silicide contact layer and planarizing the interlayer dielectric stack, patterning a plurality of contacts through the interlayer dielectric stack onto the raised source/drain regions, and, for at least some of the contacts, patterning laterally extended contact regions above the contacts, the laterally extended contact regions extending over shallow trench insulator regions neighboring the corresponding raised source/drain regions.

公开(公告)号：US10199378B2

公开(公告)日：2019-02-05

申请号：US15857202

申请日：2017-12-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Navneet Jain ,  Juhan Kim ,  Andy Nguyen ,  Mahbub Rashed

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L27/02 ,  H01L23/528 ,  H01L21/8238

Abstract: Methods for abutting two cells with different sized diffusion regions and the resulting devices are provided. Embodiments include abutting a first cell having first drain and source diffusion regions and a second cell having second drain and source diffusion regions, larger than the first diffusion regions, by: forming a dummy gate at a boundary between the two cells; forming a continuous drain diffusion region having an upper portion crossing the dummy gate and encompassing the entire first drain diffusion region and part of the second drain diffusion region and having a lower portion beginning over the dummy gate and encompassing a remainder of the second drain diffusion region; forming a continuous source diffusion region that is the mirror image of the continuous drain diffusion region; and forming a poly-cut mask over the dummy gate between, but separated from, the continuous drain and source diffusion regions.

公开(公告)号：US09893063B2

公开(公告)日：2018-02-13

申请号：US15420967

申请日：2017-01-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Navneet Jain ,  Juhan Kim ,  Andy Nguyen ,  Mahbub Rashed

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/02 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for abutting two cells with different sized diffusion regions and the resulting devices are provided. Embodiments include abutting a first cell having first drain and source diffusion regions and a second cell having second drain and source diffusion regions, larger than the first diffusion regions, by: forming a dummy gate at a boundary between the two cells; forming a continuous drain diffusion region having an upper portion crossing the dummy gate and encompassing the entire first drain diffusion region and part of the second drain diffusion region and having a lower portion beginning over the dummy gate and encompassing a remainder of the second drain diffusion region; forming a continuous source diffusion region that is the mirror image of the continuous drain diffusion region; and forming a poly-cut mask over the dummy gate between, but separated from, the continuous drain and source diffusion regions.

公开(公告)号：US20170316140A1

公开(公告)日：2017-11-02

申请号：US15140183

申请日：2016-04-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Juhan Kim ,  Mahbub Rashed

IPC: G06F17/50 ,  H01L27/02 ,  H01L23/535

CPC classification number: G06F17/5072 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11881

Abstract: At least one method, apparatus and system disclosed herein for forming a semiconductor device comprising a plurality of cells having metal features formed using triple patterning processes. An overall pattern layout is created for a first cell that is to be manufactured using a triple patterning process for forming a plurality of metal features on a metal layer. A first color metal feature is formed in the metal layer. The first color metal feature is associated with a first patterning process of the triple patterning process. A second color metal feature is formed in the metal layer. The second color metal feature is associated with a second patterning process of the triple patterning process. A third color metal feature is formed in the metal layer. The third color metal feature is associated with a third patterning process of the triple patterning process. At least one of the first, second, and third color metal features is re-colorable.

公开(公告)号：US20170063357A1

公开(公告)日：2017-03-02

申请号：US14838215

申请日：2015-08-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anurag Mittal ,  Mahbub Rashed

IPC: H03K5/14 ,  H03K19/0185 ,  G06F17/50

CPC classification number: H03K5/14 ,  G06F17/5036 ,  G06F17/5045 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/84 ,  H03K5/133 ,  H03K19/01855 ,  H03K2005/00019

Abstract: At least one method, apparatus and system disclosed involves providing a design for manufacturing a semiconductor device. An operation modeling of a semiconductor device circuit design is performed. At least one transistor is identified for providing at least one of a first voltage for forward biasing the transistor or a second voltage for reverse biasing the transistor. Selectively providing a delay for adjusting a timing associated with the transistor based upon identifying the at least one transistor for providing the at least one of a first voltage for forward biasing the transistor or a second voltage for reverse biasing.

Abstract translation: 所公开的至少一种方法，装置和系统涉及提供用于制造半导体器件的设计。 执行半导体器件电路设计的操作建模。 识别至少一个晶体管用于提供用于正向偏置晶体管的第一电压或用于反向偏置晶体管的第二电压中的至少一个。 基于识别用于提供用于正向偏置晶体管的第一电压或用于反向偏置的第二电压的至少一个晶体管，选择性地提供用于调整与晶体管相关联的定时的延迟。

公开(公告)号：US09035679B2

公开(公告)日：2015-05-19

申请号：US13886423

申请日：2013-05-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Mahbub Rashed ,  Irene Yuh-Ling Lin ,  Jongwook Kye

IPC: G06F17/50 ,  H01L23/522 ,  H01L27/02 ,  H01L27/118 ,  H01L23/528

CPC classification number: G06F17/5077 ,  H01L23/5221 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments described herein provide approaches for improving a standard cell connection for circuit routing. Specifically, provided is an IC device having a plurality of cells, a first metal layer (M1) pin coupled to a contact bar extending from a first cell of the plurality of cells, and a second metal layer (M2) wire coupled to the contact bar, wherein the contact bar extends across at least one power rail. By extending the contact bar into an open area between the plurality of cells to couple the M1 pin and the M2 wire, routing efficiency and chip scaling are improved.

Abstract translation: 本文描述的实施例提供了用于改进电路布线的标准单元连接的方法。 具体地，提供有具有多个单元的IC器件，耦合到从多个单元的第一单元延伸的接触棒的第一金属层（M1）引脚和耦合到该触点的第二金属层（M2）线 杆，其中接触杆延伸穿过至少一个电源轨。 通过将接触杆延伸到多个单电池之间的开放区域中以耦合M1引脚和M2线，提高了布线效率和芯片缩放。

公开(公告)号：US20140339647A1

公开(公告)日：2014-11-20

申请号：US13893524

申请日：2013-05-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mahbub Rashed ,  Juhan Kim ,  Yunfei Deng ,  Suresh Venkatesan

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/8238

CPC classification number: H01L29/0696 ,  G06F17/5072 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/6681 ,  H01L29/785

Abstract: One method disclosed herein includes forming first and second transistor devices in and above adjacent active regions that are separated by an isolation region, wherein the transistors comprise a source/drain region and a shared gate structure, forming a continuous conductive line that spans across the isolation region and contacts the source/drain regions of the transistors and etching the continuous conductive line to form separated first and second unitary conductive source/drain contact structures that contact the source/drain regions of the first and second transistors, respectively. A device disclosed herein includes a gate structure, source/drain regions, first and second unitary conductive source/drain contact structures, each of which contacts one of the source/drain regions, and first and second conductive vias that contact the first and second unitary conductive source/drain contact structures, respectively

Abstract translation: 本文公开的一种方法包括在由隔离区域分隔的相邻有源区域中和上方形成第一和第二晶体管器件，其中晶体管包括源极/漏极区域和共享栅极结构，形成跨越隔离的连续导电线 区域并与晶体管的源极/漏极区域接触并蚀刻连续导电线以形成分别与第一和第二晶体管的源极/漏极区域接触的分离的第一和第二整体导电源极/漏极接触结构。 本文公开的器件包括栅极结构，源极/漏极区域，第一和第二整体导电源极/漏极接触结构，其每一个接触源极/漏极区域之一，以及接触第一和第二整体的第一和第二导电通孔 导电源极/漏极接触结构

公开(公告)号：US20140258960A1

公开(公告)日：2014-09-11

申请号：US13792946

申请日：2013-03-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Navneet Jain ,  Yunfei Deng ,  Mahbub Rashed ,  David Doman ,  Qi Xiang ,  Jongwook Kye

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  Y02T10/82

Abstract: An approach and apparatus are provided for optimizing and combining different semiconductor technologies into a single graphic data system. Embodiments include generating a planar semiconductor layout design, generating a three-dimensional (e.g., FinFET) semiconductor layout design, and combining the planar design and the FinFET design in a common graphic data system.

Abstract translation: 提供了将不同半导体技术优化并组合成单个图形数据系统的方法和装置。 实施例包括生成平面半导体布局设计，产生三维（例如，FinFET）半导体布局设计，以及将平面设计和FinFET设计组合在通用图形数据系统中。

公开(公告)号：US20190333853A1

公开(公告)日：2019-10-31

申请号：US16411237

申请日：2019-05-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Juhan Kim ,  Mahbub Rashed ,  Navneet Jain

IPC: H01L23/528 ,  H01L23/50 ,  G06F17/50 ,  H01L23/522 ,  H01L27/02

Abstract: In an exemplary structure, a first conductor connects a power source to integrated circuit devices. The first conductor includes a first axis defining a first side and a second side. A second conductor, perpendicular to the first conductor, is connected to the first conductor by first vias. A third conductor, parallel to the first conductor, is connected to the second conductor by second vias. The third conductor includes a second axis defining a third side and a fourth side. The first side and the third side are aligned in a first plane perpendicular to the conductors and the second side and the fourth side are aligned in a second plane perpendicular to the conductors. The first vias contact the first conductor in only the first side. The second vias contact the third conductor in only the third side. And the second conductor is outside the second plane.