公开(公告)号：US20140258960A1

公开(公告)日：2014-09-11

申请号：US13792946

申请日：2013-03-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Navneet Jain ,  Yunfei Deng ,  Mahbub Rashed ,  David Doman ,  Qi Xiang ,  Jongwook Kye

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  Y02T10/82

Abstract: An approach and apparatus are provided for optimizing and combining different semiconductor technologies into a single graphic data system. Embodiments include generating a planar semiconductor layout design, generating a three-dimensional (e.g., FinFET) semiconductor layout design, and combining the planar design and the FinFET design in a common graphic data system.

Abstract translation: 提供了将不同半导体技术优化并组合成单个图形数据系统的方法和装置。 实施例包括生成平面半导体布局设计，产生三维（例如，FinFET）半导体布局设计，以及将平面设计和FinFET设计组合在通用图形数据系统中。

公开(公告)号：US10068806B2

公开(公告)日：2018-09-04

申请号：US15905621

申请日：2018-02-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： David C. Pritchard ,  Tuhin Guha Neogi ,  Scott Luning ,  David Doman

IPC: H01L21/8234 ,  H01L29/08 ,  H01L29/66 ,  H01L23/522 ,  H01L23/528 ,  H01L21/027 ,  H01L21/768 ,  H01L21/311 ,  H01L21/321 ,  H01L27/146

CPC classification number: H01L21/823475 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823418 ,  H01L23/522 ,  H01L23/5221 ,  H01L23/5222 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/14636 ,  H01L29/0847 ,  H01L29/66568

Abstract: At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (MOL) feature. A first location for a non-contact intersection region between a first middle of line (MOL) interconnect feature and a metal feature in a functional cell is determined. A dielectric feature is formed over the first MOL interconnect feature at the first location. The metal feature is formed over the dielectric layer, the dielectric layer providing a predetermined amount of voltage isolation between the first MOL interconnect feature and the metal feature.

公开(公告)号：US09666488B1

公开(公告)日：2017-05-30

申请号：US15095612

申请日：2016-04-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tuhin Guha Neogi ,  David Pritchard ,  Scott Luning ,  Guillaume Bouche ,  David Doman

IPC: H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/285 ,  H01L27/092 ,  H01L27/12 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L21/823814 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7838 ,  H01L29/7848

Abstract: A method of forming a silicide layer as a pass-through contact under a gate contact between p-epilayer and n-epilayer source/drains and the resulting device are provided. Embodiments include depositing a semiconductor layer over a substrate; forming a pFET gate on a p-side of the semiconductor layer and a nFET gate on a n-side of the semiconductor layer; forming a gate contact between the pFET gate and the nFET gate; forming raised source/drains on opposite sides of each of the pFET and nFET gates; and forming a metal silicide over a first raised source/drain on the p-side and over a second raised source/drain on the n-side, wherein the metal silicide extends from the first raised source/drain to the second raised source/drain and below the gate contact between the pFET and nFET gates.

公开(公告)号：US20180108571A1

公开(公告)日：2018-04-19

申请号：US15294228

申请日：2016-10-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： David C. Pritchard ,  Tuhin Guha Neogi ,  Scott Luning ,  David Doman

IPC: H01L21/8234 ,  H01L21/768 ,  H01L21/321 ,  H01L21/311 ,  H01L21/027 ,  H01L23/528 ,  H01L23/522 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L21/823475 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823418 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/14636 ,  H01L29/0847 ,  H01L29/66568

Abstract: At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (MOL) feature. A first location for a non-contact intersection region between a first middle of line (MOL) interconnect feature and a metal feature in a functional cell is determined. A dielectric feature is formed over the first MOL interconnect feature at the first location. The metal feature is formed over the dielectric layer, the dielectric layer providing a predetermined amount of voltage isolation between the first MOL interconnect feature and the metal feature.

公开(公告)号：US20180182674A1

公开(公告)日：2018-06-28

申请号：US15905621

申请日：2018-02-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： David C. Pritchard ,  Tuhin Guha Neogi ,  Scott Luning ,  David Doman

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L21/027 ,  H01L21/321 ,  H01L21/311

CPC classification number: H01L21/823475 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823418 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/14636 ,  H01L29/0847 ,  H01L29/66568

Abstract: At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (MOL) feature. A first location for a non-contact intersection region between a first middle of line (MOL) interconnect feature and a metal feature in a functional cell is determined. A dielectric feature is formed over the first MOL interconnect feature at the first location. The metal feature is formed over the dielectric layer, the dielectric layer providing a predetermined amount of voltage isolation between the first MOL interconnect feature and the metal feature.

公开(公告)号：US09947590B1

公开(公告)日：2018-04-17

申请号：US15294228

申请日：2016-10-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： David C. Pritchard ,  Tuhin Guha Neogi ,  Scott Luning ,  David Doman

IPC: H01L21/00 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/321 ,  H01L21/311 ,  H01L21/027 ,  H01L23/528 ,  H01L23/522 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L21/823475 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823418 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/14636 ,  H01L29/0847 ,  H01L29/66568

Abstract: At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (MOL) feature. A first location for a non-contact intersection region between a first middle of line (MOL) interconnect feature and a metal feature in a functional cell is determined. A dielectric feature is formed over the first MOL interconnect feature at the first location. The metal feature is formed over the dielectric layer, the dielectric layer providing a predetermined amount of voltage isolation between the first MOL interconnect feature and the metal feature.