公开(公告)号：US08975712B2

公开(公告)日：2015-03-10

申请号：US13893524

申请日：2013-05-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mahbub Rashed ,  Juhan Kim ,  Yunfei Deng ,  Suresh Venkatesan

IPC: H01L27/092 ,  H01L21/336 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/338 ,  H01L21/8238 ,  G06F17/50

CPC classification number: H01L29/0696 ,  G06F17/5072 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/6681 ,  H01L29/785

Abstract: One method disclosed herein includes forming first and second transistor devices in and above adjacent active regions that are separated by an isolation region, wherein the transistors comprise a source/drain region and a shared gate structure, forming a continuous conductive line that spans across the isolation region and contacts the source/drain regions of the transistors and etching the continuous conductive line to form separated first and second unitary conductive source/drain contact structures that contact the source/drain regions of the first and second transistors, respectively. A device disclosed herein includes a gate structure, source/drain regions, first and second unitary conductive source/drain contact structures, each of which contacts one of the source/drain regions, and first and second conductive vias that contact the first and second unitary conductive source/drain contact structures, respectively.

Abstract translation: 本文公开的一种方法包括在由隔离区域分隔的相邻有源区域中和上方形成第一和第二晶体管器件，其中晶体管包括源极/漏极区域和共享栅极结构，形成跨越隔离的连续导电线 区域并与晶体管的源极/漏极区域接触并蚀刻连续导电线以形成分别与第一和第二晶体管的源极/漏极区域接触的分离的第一和第二整体导电源极/漏极接触结构。 本文公开的器件包括栅极结构，源极/漏极区域，第一和第二整体导电源极/漏极接触结构，其每一个接触源极/漏极区域之一，以及接触第一和第二整体的第一和第二导电通孔 导电源极/漏极接触结构。

公开(公告)号：US20140327146A1

公开(公告)日：2014-11-06

申请号：US13874803

申请日：2013-05-01

Applicant: Globalfoundries Inc

Inventor： Yunfei Deng ,  Lei Yuan ,  Hidekazu Yoshida ,  Juhan Kim ,  Mahbub Rashed ,  Jongwook Kye

IPC: G06F17/50 ,  H01L23/48

CPC classification number: G06F17/5077 ,  G06F17/5072 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11831 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A design methodology for routing for an integrated circuit is disclosed. The method includes placement of cells having double diffusion breaks, which create an extended intercell region. Metal layer prohibit zones are defined to prohibit any M1 structures in the prohibit zones. Metal layer allow zones are placed adjacent to outer metal lines, and jogs are formed in the metal layer allow zones. Vias and viabars may then be applied on the jogs.

Abstract translation: 公开了用于集成电路布线的设计方法。 该方法包括放置具有双扩散断裂的电池，这产生扩展的电池间​​区域。 金属层禁止区被定义为禁止禁区内的任何M1结构。 金属层允许区域邻近外部金属线放置，并且在金属层中形成点动允许区域。 然后将通风口和viabars应用于慢跑。

公开(公告)号：US20140339647A1

公开(公告)日：2014-11-20

申请号：US13893524

申请日：2013-05-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mahbub Rashed ,  Juhan Kim ,  Yunfei Deng ,  Suresh Venkatesan

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/8238

CPC classification number: H01L29/0696 ,  G06F17/5072 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/6681 ,  H01L29/785

Abstract: One method disclosed herein includes forming first and second transistor devices in and above adjacent active regions that are separated by an isolation region, wherein the transistors comprise a source/drain region and a shared gate structure, forming a continuous conductive line that spans across the isolation region and contacts the source/drain regions of the transistors and etching the continuous conductive line to form separated first and second unitary conductive source/drain contact structures that contact the source/drain regions of the first and second transistors, respectively. A device disclosed herein includes a gate structure, source/drain regions, first and second unitary conductive source/drain contact structures, each of which contacts one of the source/drain regions, and first and second conductive vias that contact the first and second unitary conductive source/drain contact structures, respectively

Abstract translation: 本文公开的一种方法包括在由隔离区域分隔的相邻有源区域中和上方形成第一和第二晶体管器件，其中晶体管包括源极/漏极区域和共享栅极结构，形成跨越隔离的连续导电线 区域并与晶体管的源极/漏极区域接触并蚀刻连续导电线以形成分别与第一和第二晶体管的源极/漏极区域接触的分离的第一和第二整体导电源极/漏极接触结构。 本文公开的器件包括栅极结构，源极/漏极区域，第一和第二整体导电源极/漏极接触结构，其每一个接触源极/漏极区域之一，以及接触第一和第二整体的第一和第二导电通孔 导电源极/漏极接触结构

公开(公告)号：US20140258960A1

公开(公告)日：2014-09-11

申请号：US13792946

申请日：2013-03-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Navneet Jain ,  Yunfei Deng ,  Mahbub Rashed ,  David Doman ,  Qi Xiang ,  Jongwook Kye

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  Y02T10/82

Abstract: An approach and apparatus are provided for optimizing and combining different semiconductor technologies into a single graphic data system. Embodiments include generating a planar semiconductor layout design, generating a three-dimensional (e.g., FinFET) semiconductor layout design, and combining the planar design and the FinFET design in a common graphic data system.

Abstract translation: 提供了将不同半导体技术优化并组合成单个图形数据系统的方法和装置。 实施例包括生成平面半导体布局设计，产生三维（例如，FinFET）半导体布局设计，以及将平面设计和FinFET设计组合在通用图形数据系统中。

公开(公告)号：US08881083B1

公开(公告)日：2014-11-04

申请号：US13874803

申请日：2013-05-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yunfei Deng ,  Lei Yuan ,  Hidekazu Yoshida ,  Juhan Kim ,  Mahbub Rashed ,  Jongwook Kye

IPC: G06F17/50 ,  H01L23/48

CPC classification number: G06F17/5077 ,  G06F17/5072 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11831 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A design methodology for routing for an integrated circuit is disclosed. The method includes placement of cells having double diffusion breaks, which create an extended intercell region. Metal layer prohibit zones are defined to prohibit any M1 structures in the prohibit zones. Metal layer allow zones are placed adjacent to outer metal lines, and jogs are formed in the metal layer allow zones. Vias and viabars may then be applied on the jogs.

Abstract translation: 公开了用于集成电路布线的设计方法。 该方法包括放置具有双扩散断裂的电池，这产生扩展的电池间​​区域。 金属层禁止区被定义为禁止禁区内的任何M1结构。 金属层允许区域邻近外部金属线放置，并且在金属层中形成点动允许区域。 然后将通风口和viabars应用于慢跑。

公开(公告)号：US20140273474A1

公开(公告)日：2014-09-18

申请号：US13799539

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Youngtag WOO ,  Dinesh Somasekhar ,  Juhan Kim ,  Yunfei Deng ,  Jongwook Kye

IPC: H01L21/308

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L27/0207 ,  H01L27/11

Abstract: Methodology enabling a generation of an interconnection design utilizing an SIT process is disclosed. Embodiments include: providing a hardmask on a substrate; forming a mandrel layer on the hardmask including: first and second vertical portions extending along a vertical direction and separated by a horizontal distance; and a plurality of horizontal portions extending in a horizontal direction, wherein each of the horizontal portions is positioned between the first and second vertical portions and at a different position along the vertical direction; and forming a spacer layer on outer edges of the mandrel layer.

Abstract translation: 公开了能够利用SIT过程产生互连设计的方法。 实施例包括：在基板上提供硬掩模; 在所述硬掩模上形成心轴层，包括：沿着垂直方向延伸并分开水平距离的第一和第二垂直部分; 以及沿水平方向延伸的多个水平部分，其中每个水平部分位于第一和第二垂直部分之间以及沿着垂直方向的不同位置; 以及在心轴层的外边缘上形成间隔层。

公开(公告)号：US09142513B2

公开(公告)日：2015-09-22

申请号：US14645598

申请日：2015-03-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mahbub Rashed ,  Yuansheng Ma ,  Irene Lin ,  Jason Stephens ,  Yunfei Deng ,  Yuan Lei ,  Jongwook K E ,  Roderick Augur ,  Shibly Ahmed ,  Subramani Kengeri ,  Suresh Venkatesan

IPC: H01L23/538 ,  H01L29/78 ,  H01L27/092 ,  H01L27/02

CPC classification number: H01L23/5386 ,  H01L21/76895 ,  H01L21/823871 ,  H01L23/5384 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An approach for providing MOL constructs using diffusion contact structures is disclosed. Embodiments include: providing a first diffusion region in a substrate; providing, via a first lithography process, a first diffusion contact structure; providing, via a second lithography process, a second diffusion contact structure; and coupling the first diffusion contact structure to the first diffusion region and the second diffusion contact structure. Embodiments include: providing a second diffusion region in the substrate; providing a diffusion gap region between the first and second diffusion regions; providing the diffusion contact structure over the diffusion gap region; and coupling, via the diffusion contact structure, the first and second diffusion regions.

公开(公告)号：US08637214B2

公开(公告)日：2014-01-28

申请号：US13725191

申请日：2012-12-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yunfei Deng ,  Jongwook Kye

IPC: G03F1/00 ,  G03F1/70

CPC classification number: G03F1/00 ,  G03B27/42 ,  G03F7/2024 ,  H01L21/0273

Abstract: Methods are provided for fabricating a semiconductor device. One method comprises providing a first pattern having a first polygon, the first polygon having a first tonality and having a first side and a second side, the first side adjacent to a second polygon having a second tonality, and the second side adjacent to a third polygon having the second tonality, and forming a second pattern by reversing the tonality of the first pattern. The method further comprises forming a third pattern from the second pattern by converting the second polygon from the first tonality to the second tonality forming a fourth pattern from the second pattern by converting the third polygon from the first tonality to the second tonality forming a fifth pattern by reversing the tonality of the third pattern, and forming a sixth pattern by reversing the tonality of the fourth pattern.

Abstract translation: 提供了制造半导体器件的方法。 一种方法包括提供具有第一多边形的第一图案，所述第一多边形具有第一音调并且具有第一侧和第二侧，所述第一侧邻近于具有第二音调的第二多边形，并且所述第二侧相邻于第三多边形 具有第二色调的多边形，并且通过反转第一图案的色调来形成第二图案。 该方法还包括通过从第二图案将第二多边形从第一图案转换成第二色调而将第二多边形从第一色调转换成第二色调以从第二图案转换成第二色调，从第二图案形成第三图案， 通过颠倒第三图案的音调，并通过反转第四图案的音调形成第六图案。

公开(公告)号：US20150108583A1

公开(公告)日：2015-04-23

申请号：US14579628

申请日：2014-12-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mahbub Rashed ,  Johan Kim ,  Yunfei Deng ,  Suresh Venkatesan

IPC: H01L29/06 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L29/0696 ,  G06F17/5072 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/6681 ,  H01L29/785

Abstract: One method disclosed herein includes forming first and second transistor devices in and above adjacent active regions that are separated by an isolation region, wherein the transistors comprise a source/drain region and a shared gate structure, forming a continuous conductive line that spans across the isolation region and contacts the source/drain regions of the transistors and etching the continuous conductive line to form separated first and second unitary conductive source/drain contact structures that contact the source/drain regions of the first and second transistors, respectively. A device disclosed herein includes a gate structure, source/drain regions, first and second unitary conductive source/drain contact structures, each of which contacts one of the source/drain regions, and first and second conductive vias that contact the first and second unitary conductive source/drain contact structures, respectively

Abstract translation: 本文公开的一种方法包括在由隔离区域分隔的相邻有源区域中和上方形成第一和第二晶体管器件，其中晶体管包括源极/漏极区域和共享栅极结构，形成跨越隔离的连续导电线 区域并与晶体管的源极/漏极区域接触并蚀刻连续导电线以形成分别与第一和第二晶体管的源极/漏极区域接触的分离的第一和第二整体导电源极/漏极接触结构。 本文公开的器件包括栅极结构，源极/漏极区域，第一和第二整体导电源极/漏极接触结构，其每一个接触源极/漏极区域之一，以及接触第一和第二整体的第一和第二导电通孔 导电源极/漏极接触结构

公开(公告)号：US08962483B2

公开(公告)日：2015-02-24

申请号：US13799539

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Youngtag Woo ,  Dinesh Somasekhar ,  Juhan Kim ,  Yunfei Deng ,  Jongwook Kye

IPC: H01L21/3065 ,  H01L21/308 ,  G03F7/26

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L27/0207 ,  H01L27/11

Abstract: Methodology enabling a generation of an interconnection design utilizing an SIT process is disclosed. Embodiments include: providing a hardmask on a substrate; forming a mandrel layer on the hardmask including: first and second vertical portions extending along a vertical direction and separated by a horizontal distance; and a plurality of horizontal portions extending in a horizontal direction, wherein each of the horizontal portions is positioned between the first and second vertical portions and at a different position along the vertical direction; and forming a spacer layer on outer edges of the mandrel layer.

Abstract translation: 公开了能够利用SIT过程产生互连设计的方法。 实施例包括：在基板上提供硬掩模; 在所述硬掩模上形成心轴层，包括：沿着垂直方向延伸并分开水平距离的第一和第二垂直部分; 以及沿水平方向延伸的多个水平部分，其中每个水平部分位于第一和第二垂直部分之间以及沿着垂直方向的不同位置; 以及在心轴层的外边缘上形成间隔层。